Patent application number | Description | Published |
20080227250 | CMOS device with dual-EPI channels and self-aligned contacts - A CMOS device having dual-epi channels comprises a first epitaxial region formed on a substrate, a PMOS device formed on the first epitaxial region, a second epitaxial region formed on the substrate, wherein the second epitaxial region is formed from a different material than the first epitaxial region, an NMOS device formed on the second epitaxial region, and electrical contacts coupled to the PMOS and NMOS devices, wherein the electrical contacts are self-aligned. | 09-18-2008 |
20080237603 | METHOD OF FORMING CMOS TRANSISTORS WITH DUAL-METAL SILICIDE FORMED THROUGH THE CONTACT OPENINGS AND STRUCTURES FORMED THEREBY - Methods and associated structures of forming a microelectronic device are described. Those methods may include amorphizing at least one contact area of a source/drain region of a transistor structure by implanting through at least one contact opening, forming a first layer of metal on the at least one contact area, forming a second layer of metal on the first layer of metal, selectively etching a portion of the second metal layer, and annealing the at least one contact area to form at least one silicide. | 10-02-2008 |
20080237661 | ULTRA-ABRUPT SEMICONDUCTOR JUNCTION PROFILE - The present invention discloses a method including: providing a substrate; forming recessed regions adjacent to both sides of a gate on the substrate; performing an angled co-implant of a species in two steps with two different energies and two different doses into the recessed regions; forming Silicon-Germanium in the recessed regions; forming source/drain extensions adjacent to both sides of the gate with a dopant; and performing an anneal to activate the dopant. | 10-02-2008 |
20080237741 | METHODS OF FORMING IMPROVED EPI FILL ON NARROW ISOLATION BOUNDED SOURCE/DRAIN REGIONS AND STRUCTURES FORMED THEREBY - Methods and associated structures of forming a microelectronic device are described. Those methods may include plasma etching a portion of a source/drain region of a transistor, and then selectively wet etching the source drain region along a (100) plane to form at least one (111) region in the recessed source/drain region. | 10-02-2008 |
20080237742 | METHODS OF FORMING IMPROVED EPI FILL ON NARROW ISOLATION BOUNDED SOURCE/DRAIN REGIONS AND STRUCTURES FORMED THEREBY - Methods and associated structures of forming a microelectronic device are described. Those methods may include plasma etching a portion of a source/drain region of a transistor, and then selectively wet etching the source drain region along a ( | 10-02-2008 |
20090001588 | Metal and alloy silicides on a single silicon wafer - Methods and apparatus relating to a single silicon wafer having metal and alloy silicides are described. In one embodiment, two different silicides may be provided on the same wafer. Other embodiments are also disclosed. | 01-01-2009 |
20090090982 | Ultra-abrupt semiconductor junction profile - The present invention discloses a method including: providing a substrate; forming recessed regions adjacent to both sides of a gate on the substrate; performing an angled co-implant of a species in two steps with two different energies and two different doses into the recessed regions; forming Silicon-Germanium in the recessed regions; forming source/drain extensions adjacent to both sides of the gate with a dopant; and performing an anneal to activate the dopant. | 04-09-2009 |
20150179742 | ACTIVE REGIONS WITH COMPATIBLE DIELECTRIC LAYERS - A method to form a semiconductor structure with an active region and a compatible dielectric layer is described. In one embodiment, a semiconductor structure has a dielectric layer comprised of an oxide of a first semiconductor material, wherein a second (and compositionally different) semiconductor material is formed between the dielectric layer and the first semiconductor material. In another embodiment, a portion of the second semiconductor material is replaced with a third semiconductor material in order to impart uniaxial strain to the lattice structure of the second semiconductor material. | 06-25-2015 |