Patent application number | Description | Published |
20110236881 | MODULATION OF INFLUENZA VIRUS - The present invention provides, among other things, methods for the identification of compounds that are capable of modulating the activity of the influenza A virus. For example, the present methods provide platforms for identifying small molecule inhibitors that target the proton transport pathway defined at least in part by two or more of the highly conserved channel residues 27, 30, 31, 34, 37, 41, 44, and 45 of the influenza A M2 protein. In one aspect, the present invention is directed to methods comprising comparing spatial models of a plurality of test compounds with the spatial model of the pathway defined by at least two residues from among residues 27, 30, 31, 34, 37 or 41, 44, and 45 on one or more subunits of the M2 transmembrane protein of the influenza A virus to determine the spatial complementarity of each of the test compounds with the pathway; assessing the ability of the test compounds to bind to the pathway; and, based on the assessed ability of the test compounds to bind the pathway, determining the compound that modulates the activity of influenza A. | 09-29-2011 |
Patent application number | Description | Published |
20080290398 | Nonvolatile charge trap memory device having <100> crystal plane channel orientation - A nonvolatile charge trap memory device and a method to form the same are described. The device includes a channel region having a channel length with <100> crystal plane orientation. The channel region is between a pair of source and drain regions and a gate stack is disposed above the channel region. | 11-27-2008 |
20090152621 | NONVOLATILE CHARGE TRAP MEMORY DEVICE HAVING A HIGH DIELECTRIC CONSTANT BLOCKING REGION - A nonvolatile charge trap memory device is described. The device includes a substrate having a channel region and a pair of source and drain regions. A gate stack is above the substrate over the channel region and between the pair of source and drain regions. The gate stack includes a high dielectric constant blocking region. | 06-18-2009 |
20100041222 | SONOS Type Stacks for Nonvolatile ChangeTrap Memory Devices and Methods to Form the Same - A method for fabricating a nonvolatile charge trap memory device is described. The method includes forming a first oxide layer on a surface of a substrate. The first oxide layer is exposed to a first decoupled plasma nitridation process having a first bias. Subsequently, a charge-trapping layer is formed on the first oxide layer. The charge-trapping layer is exposed to an oxidation process and then to a second decoupled plasma nitridation process having a second, different, bias. | 02-18-2010 |
20120044187 | Capacitive Touch Screen - One embodiment in accordance with the invention can include a capacitive touch screen. The capacitive touch screen includes a substantially transparent substrate and a plurality of electrodes formed on the substantially transparent substrate. The plurality of electrodes are substantially parallel in a first direction and each of the plurality of electrodes includes a layer of light altering material. | 02-23-2012 |
20120044197 | Capacitive Sensor Arrangement - An example capacitive sensor arrangement includes an integrated member residing within an interior region of a capacitive sensor element. The capacitive sensor element has a first resistance to a flow of current and the integrated member has a second resistance to the flow of current that is less than the first resistance. | 02-23-2012 |
20120044198 | SELF SHIELDING CAPACITANCE SENSING PANEL - A self-shielding capacitive sensor array may include a first plurality of sensor elements and a second plurality of sensor elements, where each of the second plurality of sensor elements intersects each of the first plurality of sensor elements, such that each of the first plurality of sensor elements may be capacitively coupled with each of the second plurality of sensor elements. The first plurality of sensor elements may be configured to shield each of the second plurality of sensor elements from a noise source. | 02-23-2012 |
20130106731 | Executing Gestures with Active Stylus | 05-02-2013 |
20130106796 | Active Stylus with Capacitive Buttons and Sliders | 05-02-2013 |
20130106798 | Differential Sensing in an Active Stylus | 05-02-2013 |
20130175604 | NONVOLATILE CHARGE TRAP MEMORY DEVICE HAVING A HIGH DIELECTRIC CONSTANT BLOCKING REGION - An embodiment of a nonvolatile charge trap memory device is described. In one embodiment, the device comprises a channel comprising silicon overlying a surface on a substrate electrically connecting a first diffusion region and a second diffusion region of the memory device, and a gate stack intersecting and overlying at least a portion of the channel, the gate stack comprising a tunnel oxide abutting the channel, a split charge-trapping region abutting the tunnel oxide, and a multi-layer blocking dielectric abutting the split charge-trapping region. The split charge-trapping region includes a first charge-trapping layer comprising a nitride closer to the tunnel oxide, and a second charge-trapping layer comprising a nitride overlying the first charge-trapping layer. The multi-layer blocking dielectric comprises at least a high-K dielectric layer. | 07-11-2013 |
20130307053 | MEMORY TRANSISTOR WITH MULTIPLE CHARGE STORING LAYERS AND A HIGH WORK FUNCTION GATE ELECTRODE - A semiconductor devices including non-volatile memories and methods of fabricating the same to improve performance thereof are provided. Generally, the device includes a memory transistor comprising a polysilicon channel region electrically connecting a source region and a drain region formed in a substrate, an oxide-nitride-nitride-oxide (ONNO) stack disposed above the channel region, and a high work function gate electrode formed over a surface of the ONNO stack. In one embodiment the ONNO stack includes a multi-layer charge-trapping region including an oxygen-rich first nitride layer and an oxygen-lean second nitride layer disposed above the first nitride layer. Other embodiments are also disclosed. | 11-21-2013 |
20140103418 | SONOS TYPE STACKS FOR NONVOLATILE CHANGETRAP MEMORY DEVICES AND METHODS TO FORM THE SAME - A method for fabricating a nonvolatile charge trap memory device is described. The method includes forming a first oxide layer on a surface of a substrate. The first oxide layer is exposed to a first decoupled plasma nitridation process having a first bias. Subsequently, a charge-trapping layer is formed on the first oxide layer. The charge-trapping layer is exposed to an oxidation process and then to a second decoupled plasma nitridation process having a second, different, bias. | 04-17-2014 |
20140264551 | MEMORY TRANSISTOR WITH MULTIPLE CHARGE STORING LAYERS AND A HIGH WORK FUNCTION GATE ELECTRODE - A memory device is described. Generally, the device includes a memory transistor and a metal oxide semiconductor (MOS) logic transistor. The memory transistor includes: a channel region electrically connecting a source region and a drain region, the channel region comprising polysilicon; an oxide-nitride-nitride-oxide (ONNO) stack disposed above the channel region, the ONNO stack comprising a multi-layer charge-trapping region including an oxygen-rich first nitride layer and an oxygen-lean second nitride layer disposed above the first nitride layer; and a gate electrode comprising doped polysilicon formed over a surface of the ONNO stack. The MOS logic transistor includes a gate oxide and a gate electrode comprising doped polysilicon. Other embodiments are also described. | 09-18-2014 |
20150041880 | MEMORY TRANSISTOR WITH MULTIPLE CHARGE STORING LAYERS AND A HIGH WORK FUNCTION GATE ELECTRODE - A semiconductor device includes an oxide-nitride-oxide (ONO) dielectric stack on a surface of a substrate, and a high work function gate electrode formed over a surface of the ONO dielectric stack. The ONO dielectric stack includes a multi-layer charge storage layer including a silicon-rich, oxygen-lean top silicon nitride layer and an oxygen-rich bottom silicon nitride layer. The high work function gate electrode includes a P+ doped polysilicon layer. | 02-12-2015 |
20150084648 | Capacitive Sensor Arrangement - A capacitive sensor includes a capacitive sensor element and a conductor. The conductor includes a first end and a second end, the first end is coupled to the capacitive sensor element at a first location of the capacitive sensor element and the second end is coupled to the capacitive sensor element at a second location of the capacitive sensor element. The conductor includes a first conductivity that is higher than a second conductivity of the capacitive sensor element. | 03-26-2015 |
20150160756 | Hybrid Capacitive Touch System Design - In one embodiment, a system includes a touch sensor comprising first and second lines of conductive material inside and outside the touch sensor and third lines of conductive material outside the touch sensor and disposed between first lines of conductive material outside the touch sensor and the second lines of conductive material outside the touch sensor. The system further includes logic that is configured when executed to apply a ground signal to the third set of lines of conductive material and sense touch inputs at the touch sensor using mutual-capacitive touch sensing in response to determining to operate in a mutual-capacitive mode of operation, and apply a voltage signal to the third set of lines of conductive material and sense touch inputs at the touch sensor using self-capacitive touch sensing in response to determining to operate in a self-capacitive mode of operation. | 06-11-2015 |
20160104789 | SONOS Type Stacks for Nonvolatile ChangeTrap Memory Devices and Methods to Form the Same - A method includes forming a first oxide layer. The method further includes etching a portion of the first oxide layer using a first decoupled plasma nitridation process. The method includes forming. subsequent to the etching, a charge-trapping layer on the first oxide layer. | 04-14-2016 |