# Polig

## Raphael Polig, Boeblingen DE

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20110310680 | Interleave Memory Array Arrangement - A memory array includes a plurality of memory cells, wherein each cell of the plurality of memory cells is defined by a row and a column, wherein each row includes a unique identifying address, and wherein each column is associated with one of two sets, the columns arranged such that a column associated with a first set is adjacent to a column of a second set. | 12-22-2011 |

## Raphael Polig, Reutlingen DE

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20120008379 | GLOBAL BIT LINE RESTORE BY MOST SIGNIFICANT BIT OF AN ADDRESS LINE - An SRAM circuitry having SRAM cells for storing at least one data word of a length of at least one bit is provided. Each bit of the data words is stored in an assigned SRAM cell, wherein the SRAM circuitry comprises address lines for addressing the at least one data word, a decoding unit for decoding the address signals on the address lines to generate a word line signals on a word line per addressed word, a local bit line to be coupled to SRAM cells of different data words with different addresses, a global bit line to be coupled to the local bit line, and a global bit line restore unit for pre-charging the global bit line. The global bit line restore unit is configured for being triggered by a trigger signal based on the address signal of one of the decoded address lines. | 01-12-2012 |

## Raphael Polig, Dietikon CH

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20120174051 | Method and System for Generating a Placement Layout of a VLSI Circuit Design - A method and a system for generating a placement layout is disclosed. The method includes receiving one or more user provided schematic with circuit data, placement parameters of circuit elements, default values, and user specified function calls and variables for calculating placement parameters; evaluating variables and function calls to discrete placement parameters; evaluating justification values and adjusting relative parameter values; calculating absolute placement coordinates for all cells from relative placement parameters for each instance; adjusting placement coordinates for alignment options; and generating a layout/hierarchical layout with placement circuit elements based on the calculated absolute placement coordinates. | 07-05-2012 |

20140130004 | INTEGRATED CIRCUIT SCHEMATICS HAVING IMBEDDED SCALING INFORMATION FOR GENERATING A DESIGN INSTANCE - A non-transitory computer-readable memory including first data representative of a topology of a circuit including a first circuit element and a second circuit element, and second data representative of a scaling rule for the first circuit element as a function of the second circuit element. A data processing method comprising retrieving first data representative of a topology of a circuit comprising a first circuit element and a second circuit element from a memory, retrieving second data representative of a scaling rule for the first circuit element as a function of the second circuit element from the memory, receiving a user input representative of a scaling factor, generating third data representative of an instance of the second circuit element using the scaling factor, and generating data representative of an instance of the first circuit element using the scaling factor, the scaling rule and the third data. | 05-08-2014 |

20140192602 | DEFECTIVE MEMORY COLUMN REPLACEMENT WITH LOAD ISOLATION - Exemplary embodiments of the present invention disclose a method and system for substituting a group of memory cells for a defective group of memory cells in a memory. In a step, an exemplary embodiment replaces a signal path to a group of defective memory cells with a signal path to a redundant group of memory cells. In another step, an exemplary embodiment isolates the signal path to the redundant group of memory cells from a load imposed by the signal path to the replaced group of defective memory cells. | 07-10-2014 |

20140244554 | NON-DETERMINISTIC FINITE STATE MACHINE MODULE FOR USE IN A REGULAR EXPRESSION MATCHING SYSTEM - A non-deterministic finite state machine module for use in a regular expression matching system. The system includes a computational unit implementing a non-deterministic finite state machine representing a regular expression, wherein the computational unit is configured to: receive an input data stream, wherein an occurrence of the regular expression is determined, and an activation signal; process the input data stream with respect to the non-deterministic finite state machine depending on the activation signal; and provide at least one branch data output for initializing an additional non-deterministic finite state machine module if the processing of an element of the input data stream according to the non-deterministic finite state machine results in a branching of a processing thread. | 08-28-2014 |

## Raphael C. Polig, Dietikon CH

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20150234781 | CONJUGATE GRADIENT SOLVERS FOR LINEAR SYSTEMS - A conjugate gradient solver apparatus is provided for generating data defining a solution vector x for a linear system represented by Ax=b where A is a predetermined matrix and b is a predetermined vector. The apparatus includes solver circuitry and a precision controller. The solver circuitry processes input data, defining said matrix A and vector b, in accordance with an iterative conjugate gradient method to generate said data defining the solution vector x. The solver circuitry is adapted to process data items, corresponding to vectors used in said conjugate gradient method, having a variable fixed-point data format. The precision controller determines the fixed-point data formats of respective said data items adaptively during progress of the conjugate gradient method in the solver circuitry. | 08-20-2015 |

20150234783 | ITERATIVE REFINEMENT APPARATUS - An iterative refinement apparatus configured to generate data defining a solution vector x for a linear system represented by Ax=b, where A is a predetermined matrix and b is a predetermined vector. An outer solver processes input data, defining the matrix A and vector b, in accordance with an outer loop of an iterative refinement method to generate said data defining the solution vector x. An inner solver processes data items in accordance with an inner loop of the iterative refinement method. The inner solver is configured to process said data items having variable bit-width and data format. A precision controller determines the bit-widths and data formats of the data items adaptively in dependence on the results of the processing steps of the iterative refinement method; the precision controller configured to control operation of the inner solver for processing said data items with the bit-widths and data formats. | 08-20-2015 |