Patent application number | Description | Published |
20100052072 | DUAL GATE STRUCTURE ON A SAME CHIP FOR HIGH-K METAL GATE TECHNOLOGY - A semiconductor device and method for fabricating a semiconductor device is disclosed. The method includes providing semiconductor substrate having a first region and a second region, forming a high-k dielectric layer over the semiconductor substrate, forming a capping layer over the high-k dielectric layer, forming a metal layer over the capping layer, removing the metal layer and capping layer in the second region, forming a polysilicon layer over the metal layer in the first region and over the high-k dielectric layer in the second region, and forming an active device with the metal layer in the first region and forming a passive device without the metal layer in the second region. | 03-04-2010 |
20120280323 | DEVICE HAVING A GATE STACK - A device includes a drain, a source, and a gate stack. The gate stack has a gate dielectric layer, a gate conductive layer immediately on top of the gate dielectric layer, and first gate and a second gate layer that are immediately on top of the gate conductive layer. The first gate layer has a first resistance higher than a second resistance of the second gate layer. The second gate layer is conductive, is electrically coupled with the gate conductive layer, and has a contact terminal configured to serve as a gate contact terminal for the device. Fabrication methods of the gate stack are also disclosed. | 11-08-2012 |
20130032884 | INTEGRATED CIRCUIT DEVICE HAVING DEFINED GATE SPACING AND METHOD OF DESIGNING AND FABRICATING THEREOF - A device, and method of fabricating and/or designing such a device, including a first gate structure having a width (W) and a length (L) and a second gate structure separated from the first gate structure by a distance greater than: (√{square root over (W*W+L*L)})/10. The second gate structure is a next adjacent gate structure to the first gate structure. A method and apparatus for designing an integrated circuit including implementing a design rule defining the separation of gate structures is also described. In embodiments, the distance of separation is implemented for gate structures that are larger relative to other gate structures on the substrate (e.g., greater than 3 μm | 02-07-2013 |
20130234254 | METHOD OF HYBRID HIGH-K/METAL-GATE STACK FABRICATION - A process fabricating a semiconductor device with a hybrid HK/metal gate stack fabrication is disclosed. The process includes providing a semiconductor substrate having a plurality of isolation features between a PFET region and a NFET region, and forming gate stacks on the semiconductor substrate. In the PFET region, the gate stack is formed as a HK/metal gate. In the NFET region, the gate stack is formed as a polysilicon gate. A high-resistor is also formed on the semiconductor substrate by utilizing another polysilicon gate. | 09-12-2013 |
20130285150 | DEVICE AND METHODS FOR HIGH-K AND METAL GATE STACKS - A semiconductor device having five gate stacks on different regions of a substrate and methods of making the same are described. The device includes a semiconductor substrate and isolation features to separate the different regions on the substrate. The different regions include a p-type field-effect transistor (pFET) core region, an input/output pFET (pFET IO) region, an n-type field-effect transistor (nFET) core region, an input/output nFET (nFET IO) region, and a high-resistor region. | 10-31-2013 |
20130285151 | DEVICE AND METHODS FOR HIGH-K AND METAL GATE STACKS - A semiconductor device having five gate stacks on different regions of a substrate and methods of making the same are described. The device includes a semiconductor substrate and isolation features to separate the different regions on the substrate. The different regions include a p-type field-effect transistor (pFET) core region, an input/output pFET (pFET IO) region, an n-type field-effect transistor (nFET) core region, an input/output nFET (nFET IO) region, and a high-resistor region. | 10-31-2013 |
20140045310 | METHOD OF MAKING STRUCTURE HAVING A GATE STACK - A method includes removing a first portion of a gate layer of a structure. The structure includes a drain region, a source region, and a gate stack, and the gate stack includes a gate dielectric layer, a gate conductive layer directly on the gate dielectric layer, and the gate layer directly on the gate conductive layer. A drain contact region is formed on the drain region, and a source contact region is formed on the source region. A conductive region is formed directly on the gate conductive layer and adjacent to a second portion of the gate layer. A gate contact terminal is formed in contact with the conductive region. | 02-13-2014 |
20140103429 | Method and Structure to Boost MOSFET Performance and NBTI - The present disclosure provides one embodiment of a method forming a p-type field effect transistor (pFET) structure. The method includes forming a mask layer on a semiconductor substrate, the mask layer including an opening that exposes a semiconductor region of the semiconductor substrate within the opening; forming a n-type well (n-well) in the semiconductor region by performing an ion implantation of a n-type dopant to the semiconductor substrate through the opening of the mask layer; and performing a germanium (Ge) channel implantation to the semiconductor substrate through the opening of the mask layer, forming a Ge channel implantation region in the n-well. | 04-17-2014 |
20140183648 | Semiconductor Structures and Methods of Forming the Same - A structure and method of forming the structure is disclosed. According to an embodiment, a structure includes three devices in respective three regions of a substrate. The first device comprises a first gate stack, and the first gate stack comprises a first dielectric layer. The second device comprises a second gate stack, and the second gate stack comprises a second dielectric layer. The third device comprises a third gate stack, and the third gate stack comprises a third dielectric layer. A thickness of the third dielectric layer is less than a thickness of the second dielectric layer, and the thickness of the second dielectric layer is less than a thickness of the first dielectric layer. A gate length of the third gate stack differs in amount from a gate length of the first gate stack and a gate length of the second gate stack. | 07-03-2014 |
20140203373 | DEVICE AND METHODS FOR HIGH-K AND METAL GATE STACKS - A semiconductor device having five gate stacks on different regions of a substrate and methods of making the same are described. The device includes a semiconductor substrate and isolation features to separate the different regions on the substrate. The different regions include a p-type field-effect transistor (pFET) core region, an input/output pFET (pFET IO) region, an n-type field-effect transistor (nFET) core region, an input/output nFET (nFET IO) region, and a high-resistor region. | 07-24-2014 |
20140246732 | Circuit Incorporating Multiple Gate Stack Compositions - An integrated circuit having multiple different device gate configurations and a method for fabricating the circuit are disclosed. An exemplary embodiment of forming the circuit includes receiving a substrate having a first device region, a second device region, and a third device region. A first interfacial layer is formed over at least a portion of each of the first device region, the second device region, and the third device region. The first interfacial layer is patterned to define a gate stack within the third device region. A second interfacial layer is formed over at least a portion of the second device region. The second interfacial layer is patterned to define a gate stack within the second device region. A third interfacial layer is formed over at least a portion of the first device region. The third interfacial layer defines a gate stack within the first device region. | 09-04-2014 |
20140332893 | Integrated Circuit Device Having Defined Gate Spacing And Method Of Designing And Fabricating Thereof - A device, and method of fabricating and/or designing such a device, including a first gate structure having a width (W) and a length (L) and a second gate structure separated from the first gate structure by a distance greater than: (√{square root over (W*W+L*L)})/10. The second gate structure is a next adjacent gate structure to the first gate structure. A method and apparatus for designing an integrated circuit including implementing a design rule defining the separation of gate structures is also described. In embodiments, the distance of separation is implemented for gate structures that are larger relative to other gate structures on the substrate (e.g., greater than 3 μm | 11-13-2014 |
20150118809 | METHOD OF MAKING STRUCTURE HAVING A GATE STACK - A method includes removing a first portion of a gate layer of a first transistor and leaving a second portion of the gate layer. The first transistor includes a drain region, a source region, and a gate stack, and the gate stack includes a gate dielectric layer, a gate conductive layer over the gate dielectric layer, and the gate layer directly on the gate conductive layer. The method includes removing a gate layer of a second transistor and forming a conductive region at a region previously occupied by the first portion of the gate layer of the first transistor, the unit resistance of the conductive region being less than that of the gate layer of the first transistor. | 04-30-2015 |
20150214115 | DEVICE AND METHODS FOR HIGH-K AND METAL GATE STACKS - A method for fabricating a semiconductor device includes providing a semiconductor substrate having regions for an n-type field-effect transistor (nFET) core, an input/output nFET (nFET IO), a p-type field-effect transistor (pFET) core, an input/output pFET (pFET IO), and a high-resistor, forming an oxide layer on the IO regions of the substrate, forming an interfacial layer on the substrate and the oxide layer, depositing a high-k (HK) dielectric layer on the interfacial layer, depositing a first capping layer of a first material on the HK dielectric layer, depositing a second capping layer of a second material on the HK dielectric layer and on the first capping layer, depositing a work function (WF) metal layer on the second capping layer, depositing a polysilicon layer on the WF metal layer, and forming gate stacks on the regions of the substrate. | 07-30-2015 |
20150255352 | Semiconductor Structures and Methods of Forming the Same - A method of forming a semiconductor structure may include: forming a first dielectric layer having a first thickness over a substrate; removing a first portion of the first dielectric layer to expose a second region of the substrate; forming a second dielectric layer having a second thickness over the second region of the substrate; removing a second portion of the first dielectric layer to expose a third region of the substrate; forming a third dielectric layer having a third thickness over the third region of the substrate; and forming a first plurality of gate stacks comprising the first dielectric layer in a first region of the substrate, a second plurality of gate stacks comprising the second dielectric layer in the second region of the substrate, and a third plurality of gate stacks comprising the third dielectric layer in the third region of the substrate. | 09-10-2015 |
Patent application number | Description | Published |
20120047303 | DOCKING STATION - A docking station includes a multiplexer. The multiplexer includes a first input end, a second input end, and an encode system. The encode system is connected to the second input end, and configured to generate an encoding according to a connection status of the second input end. The encode system is configured to generate a first encoding, when a first peripheral device is connected to the second input end, to switch the multiplexer to a first state, in which the second input end is on and the first input end is off. The encode system is further configured to generate a second encoding, when the first peripheral device is not connected to the second input end, to switch the multiplexer to a second state, in which the second input end is off and the first input end is on. | 02-23-2012 |
20120056611 | CONNECTION DETECTION CIRCUIT - A connection detection circuit includes a first detection circuit and a second detection circuit. The first detection circuit includes a first comparator and a first detection pin connected to the first comparator. The first comparator is adapted to compare a first voltage level on the first detection pin with a first reference voltage. The second detection circuit includes a second detection pin. The second detection pin is adapted to connect to the first detection pin to vary the first voltage level on the first detection pin to switch an first transistor output when the connection of the first detection circuit and the second detection circuit is achieved. | 03-08-2012 |
20120058654 | CONNECTOR ASSEMBLY - A connector assembly for connecting a peripheral device to a computer includes a male connector having a plurality of first connecting pins and a female connector having a plurality of second connecting pins. The plurality of first connecting pins is configured to connect to the peripheral device. The plurality of second connecting pins is configured to connect to the computer. The plurality of second connecting pins is defined on the first circuit board in a second row and a third row. The plurality of second connecting pins comprises a plurality of differential pairs, and each differential pair comprises two differential transmission lines. The two differential transmission lines of each of the plurality of differential pairs are defined on a single row of the second and third rows. | 03-08-2012 |
20120062309 | POWER SUPPLY CIRCUIT - A power supply circuit for protecting a battery from current leakage when the battery is not in use includes a control signal input circuit and a switch circuit. The control signal input circuit receives a first control signal from a chip and output a second control signal. The switch circuit receives the second control signal and turns on or off an electronic connection between the battery and the chip. Wherein when the battery is not in use and not being charged by the adaptor, there is a possibility of current leakage from the battery. In such case, the switch circuit turns off the electronic connection between the battery and the chip, and the battery does not provide power to the chip. | 03-15-2012 |
20120162531 | HDMI AND VGA COMPATIBLE INTERFACE CIRCUIT - A signal transmitting circuit includes a HDMI signal transmitting unit adapted to output a HDMI signal, a VGA signal transmitting unit adapted to output a VGA signal, a VGA signal processing unit, and a transmitting control unit. The VGA signal processing unit is connected to the VGA signal transmitting unit. The VGA signal processing unit is adapted to receive the VGA signal from the VGA signal transmitting unit, and include a detection signal into the VGA signal to form a combination signal. A transmitting control unit is connected to the VGA signal processing unit and the HDMI signal transmitting unit. The transmitting control unit is adapted to receive the combination signal and the VGA signal, to distinguish the combination signal and the VGA signal, and to output the combination signal and the VGA signal to the appropriate receivers. | 06-28-2012 |