Patent application number | Description | Published |
20100099100 | 'ULTRA-HIGH MULTIPLEX ANALYTICAL SYSTEMS AND METHODS" - Apparatus, systems and methods for use in analyzing discrete reactions at ultra high multiplex with reduced optical noise, and increased system flexibility. Apparatus include substrates having integrated optical components that increase multiplex capability by one or more of increasing density of reaction regions, improving transmission of light to or collection of light from discrete reactions regions. Integrated optical components include reflective optical elements which re-direct illumination light and light emitted from the discrete regions to more efficiently collect emitted light. Particularly preferred applications include single molecule reaction analysis, such as polymerase mediated template dependent nucleic acid synthesis and sequence determination. | 04-22-2010 |
20100176489 | Microelectromechanical systems structures and self-aligned harpss fabrication processes for producing same - Disclosed are one-port and two-port microelectromechanical structures including variable capacitors, switches, and filter devices. High aspect-ratio micromachining is used to implement low-voltage, large value tunable and fixed capacitors, and the like. Tunable capacitors can move in the plane of the substrate by the application of DC voltages and achieve greater than 240 percent of tuning. Exemplary microelectromechanical apparatus comprises a single crystalline silicon substrate, and a conductive structure laterally separated from the single crystalline silicon substrate by first and second high aspect ratio gaps of different size, wherein at least one of the high aspect ratio gaps has an aspect ratio of at least 30:1, and is vertically anchored to the single crystalline silicon substrate by way of silicon nitride. | 07-15-2010 |
20110121412 | PLANAR MICROSHELLS FOR VACUUM ENCAPSULATED DEVICES AND DAMASCENE METHOD OF MANUFACTURE - Low temperature, multi-layered, planar microshells for encapsulation of devices such as MEMS and microelectronics. The microshells include a planar perforated pre-sealing layer, below which a non-planar sacrificial layer is accessed, and a sealing layer to close the perforation in the pre-sealing layer after the sacrificial material is removed. In an embodiment, the pre-sealing layer has perforations formed with a damascene process to be self-aligned to the chamber below the microshell. The sealing layer may include a nonhermetic layer to physically occlude the perforation and a hermetic layer over the nonhermetic occluding layer to seal the perforation. In a particular embodiment, the hermetic layer is a metal which is electrically coupled to a conductive layer adjacent to the microshell to electrically ground the microshell. | 05-26-2011 |
20110121415 | PLANAR MICROSHELLS FOR VACUUM ENCAPSULATED DEVICES AND DAMASCENE METHOD OF MANUFACTURE - Low temperature, multi-layered, planar microshells for encapsulation of devices such as MEMS and microelectronics. The microshells include a planar perforated pre-sealing layer, below which a non-planar sacrificial layer is accessed, and a sealing layer to close the perforation in the pre-sealing layer after the sacrificial material is removed. In an embodiment, the pre-sealing layer has perforations formed with a damascene process to be self-aligned to the chamber below the microshell. The sealing layer may include a nonhermetic layer to physically occlude the perforation and a hermetic layer over the nonhermetic occluding layer to seal the perforation. In a particular embodiment, the hermetic layer is a metal which is electrically coupled to a conductive layer adjacent to the microshell to electrically ground the microshell. | 05-26-2011 |
20110121416 | PLANAR MICROSHELLS FOR VACUUM ENCAPSULATED DEVICES AND DAMASCENE METHOD OF MANUFACTURE - Low temperature, multi-layered, planar microshells for encapsulation of devices such as MEMS and microelectronics. The microshells include a planar perforated pre-sealing layer, below which a non-planar sacrificial layer is accessed, and a sealing layer to close the perforation in the pre-sealing layer after the sacrificial material is removed. In an embodiment, the pre-sealing layer has perforations formed with a damascene process to be self-aligned to the chamber below the microshell. The sealing layer may include a nonhermetic layer to physically occlude the perforation and a hermetic layer over the nonhermetic occluding layer to seal the perforation. In a particular embodiment, the hermetic layer is a metal which is electrically coupled to a conductive layer adjacent to the microshell to electrically ground the microshell. | 05-26-2011 |
20110222179 | MICROMIRROR ARRAYS HAVING SELF ALIGNED FEATURES - Methods, arrays, and systems for the optical analysis of multiple chemical, biological, or biochemical reactions are provided. The invention includes methods for producing arrays of micromirrors on transparent substrates, each micromirror comprising a nanostructure or optical confinement on its top. The arrays are produced by a process in which lateral dimensions of both the nanostructures and micromirrors are defined in a single step, allowing for control of the relative placement of the features on the substrate, minimizing the process-related defects, allowing for improved optical performance and consistency. In some aspects, the invention provides methods of selectively etching large features on a substrate while not concurrently etching small features. In some aspects, the invention provides methods of etching large features on a substrate using hard mask materials. | 09-15-2011 |
20110257040 | NANOSCALE APERTURES HAVING ISLANDS OF FUNCTIONALITY - Methods, compositions and arrays for non-random loading of single analyte molecules into array structures are provided. Arrays of confined regions are produced wherein each confined region comprises a single island within the confined region. The island can be selectively functionalized with a coupling agent to couple a single molecule of interest within the confined region. | 10-20-2011 |
20130023039 | HIGH MULTIPLEX ARRAYS AND SYSTEMS - Apparatus, systems and methods for use in analyzing discrete reactions at ultra high multiplex with reduced optical noise, and increased system flexibility. Apparatus include substrates having integrated optical components that increase multiplex capability by one or more of increasing density of reaction regions, improving transmission of light to or collection of light from discrete reactions regions. Integrated optical components include reflective optical elements which re-direct illumination light and light emitted from the discrete regions to more efficiently collect emitted light. Particularly preferred applications include single molecule reaction analysis, such as polymerase mediated template dependent nucleic acid synthesis and sequence determination. | 01-24-2013 |
20130177274 | STRUCTURES FORMED USING MONOCRYSTALLINE SILICON AND/OR OTHER MATERIALS FOR OPTICAL AND OTHER APPLICATIONS - An interposer includes grooves ( | 07-11-2013 |
20130177281 | OPTICAL INTERPOSER - An optical interposer includes grooves ( | 07-11-2013 |
20140017878 | METHOD OF PROCESSING A DEVICE SUBSTRATE - Methods of processing a device substrate are disclosed herein. In one embodiment, a method of processing a device substrate can include bonding a first surface of a device substrate to a carrier with a polymeric material. The device substrate may have a plurality of first openings extending from the first surface towards a second surface of the device substrate opposite from the first surface. Then, material can be removed at the second surface of the device substrate, wherein at least some of the first openings communicate with the second surface at least one of before or after performing the removal of the material. Then, at least a portion of the polymeric material disposed between the first surface and the carrier substrate can be exposed to a substance through at least some first openings to debond the device substrate from the carrier substrate. | 01-16-2014 |
20140036454 | BVA INTERPOSER - A method for making an interposer includes forming a plurality of wire bonds bonded to one or more first surfaces of a first element. A dielectric encapsulation is formed contacting an edge surface of the wire bonds which separates adjacent wire bonds from one another. Further processing comprises removing at least portions of the first element, wherein the interposer has first and second opposite sides separated from one another by at least the encapsulation, and the interposer having first contacts and second contacts at the first and second opposite sides, respectively, for electrical connection with first and second components, respectively, the first contacts being electrically connected with the second contacts through the wire bonds. | 02-06-2014 |
20140054763 | THIN WAFER HANDLING AND KNOWN GOOD DIE TEST METHOD - A method of attaching a microelectronic element to a substrate can include aligning the substrate with a microelectronic element, the microelectronic element having a plurality of spaced-apart electrically conductive bumps each including a bond metal, and reflowing the bumps. The bumps can be exposed at a front surface of the microelectronic element. The substrate can have a plurality of spaced-apart recesses extending from a first surface thereof. The recesses can each have at least a portion of one or more inner surfaces that are non-wettable by the bond metal of which the bumps are formed. The reflowing of the bumps can be performed so that at least some of the bond metal of each bump liquefies and flows at least partially into one of the recesses and solidifies therein such that the reflowed bond material in at least some of the recesses mechanically engages the substrate. | 02-27-2014 |
20140167267 | METHOD AND STRUCTURES FOR HEAT DISSIPATING INTERPOSERS - A method for making an interconnect element includes depositing a thermally conductive layer on an in-process unit. The in-process unit includes a semiconductor material layer defining a surface and edges surrounding the surface, a plurality of conductive elements, each conductive element having a first portion extending through the semiconductor material layer and a second portion extending from the surface of the semiconductor material layer. Dielectric coatings extend over at least the second portion of each conductive element. The thermally conductive layer is deposited on the in-process unit at a thickness of at least 10 microns so as to overlie a portion of the surface of the semiconductor material layer between the second portions of the conductive elements with the dielectric coatings positioned between the conductive elements and the thermally conductive layer. | 06-19-2014 |
20140175654 | SURFACE MODIFIED TSV STRUCTURE AND METHODS THEREOF - Microelectronic elements and methods of their manufacture are disclosed. A microelectronic element may include a substrate including an opening extending through a semiconductor region of the substrate, a dielectric layer cover a wall of the opening within at least a first portion of the opening, a first metal disposed within the first portion of the opening, a second metal disposed within a second portion of the opening. The second metal may form at least part of a contact of the microelectronic element. | 06-26-2014 |
20140179099 | METHODS AND STRUCTURE FOR CARRIER-LESS THIN WAFER HANDLING - Methods of forming a microelectronic assembly and the resulting structures and devices are disclosed herein. In one embodiment, a method of forming a microelectronic assembly includes removing material exposed at portions of a surface of a substrate to form a processed substrate having a plurality of thinned portions separated by integral supporting portions of the processed substrate having a thickness greater than a thickness of the thinned portions, at least some of the thinned portions including a plurality of electrically conductive interconnects extending in a direction of the thicknesses of the thinned portions and exposed at the surface; and removing the supporting portions of the substrate to sever the substrate into a plurality of individual thinned portions, at least some individual thinned portions including the interconnects. | 06-26-2014 |
20140240938 | CARRIER-LESS SILICON INTERPOSER - An interposer can have conductive elements at a first side and terminals at a second side opposite therefrom, for connecting with a microelectronic element and a second component, respectively. The component can include a first element having a thermal expansion coefficient less than 10 ppm/° C., and an insulating second element, with a plurality of openings extending from the second side through the second element towards the first element. Conductive structure extending through the openings in the second element and through the first element electrically connects the terminals with the conductive elements. | 08-28-2014 |
20140315384 | METHOD OF PROCESSING A DEVICE SUBSTRATE - Methods of processing a device substrate are disclosed herein. In one embodiment, a method of processing a device substrate can include bonding a first surface of a device substrate to a carrier with a polymeric material. The device substrate may have a plurality of first openings extending from the first surface towards a second surface of the device substrate opposite from the first surface. Then, material can be removed at the second surface of the device substrate, wherein at least some of the first openings communicate with the second surface at least one of before or after performing the removal of the material. Then, at least a portion of the polymeric material disposed between the first surface and the carrier substrate can be exposed to a substance through at least some first openings to debond the device substrate from the carrier substrate. | 10-23-2014 |
20140339702 | METAL PVD-FREE CONDUCTING STRUCTURES - Structures and methods of forming the same are disclosed herein. In one embodiment, a structure can comprise a region having first and second oppositely facing surfaces. A barrier region can overlie the region. An alloy region can overlie the barrier region. The alloy region can include a first metal and one or more elements selected from the group consisting of silicon (Si), germanium (Ge), indium (Id), boron (B), arsenic (As), antimony (Sb), tellurium (Te), or cadmium (Cd). | 11-20-2014 |
20150053641 | PROCESS FOR MAKING HIGH MULTIPLEX ARRAYS - Processes for making high multiplex arrays for use in analyzing discrete reactions at ultra high multiplex with reduced optical noise, and increased system flexibility. The high multiplex arrays include substrates having integrated optical components that increase multiplex capability by one or more of increasing density of reaction regions, improving transmission of light to or collection of light from discrete reactions regions. Integrated optical components include reflective optical elements which re-direct illumination light and light emitted from the discrete regions to more efficiently collect emitted light. Particularly preferred applications include single molecule reaction analysis, such as polymerase mediated template dependent nucleic acid synthesis and sequence determination. | 02-26-2015 |