Patent application number | Description | Published |
20080215861 | METHOD AND APPARATUS FOR EFFICIENT RESOURCE UTILIZATION FOR PRESCIENT INSTRUCTION PREFETCH - Embodiments of an apparatus, system and method enhance the efficiency of processor resource utilization during instruction prefetching via one or more speculative threads. Renamer logic and a map table are utilized to perform filtering of instructions in a speculative thread instruction stream. The map table includes a yes-a-thing bit to indicate whether the associated physical register's content reflects the value that would be computed by the main thread. A thread progress beacon table is utilized to track relative progress of a main thread and a speculative helper thread. Based upon information in the thread progress beacon table, the main thread may effect termination of a helper thread that is not likely to provide a performance benefit for the main thread. | 09-04-2008 |
20100211940 | Post-pass binary adaptation for software-based speculative precomputation - The latencies associated with cache misses or other long-latency instructions in a main thread are decreased through the use of a simultaneous helper thread. The helper thread is a speculative prefetch thread to perform a memory prefetch for the main thread. The instructions for the helper thread are dynamically incorporated into the main thread binary during post-pass operation of a compiler. | 08-19-2010 |
20100332811 | SPECULATIVE MULTI-THREADING FOR INSTRUCTION PREFETCH AND/OR TRACE PRE-BUILD - The latencies associated with retrieving instruction information for a main thread are decreased through the use of a simultaneous helper thread. The helper thread is a speculative prefetch thread to perform instruction prefetch and/or trace pre-build for the main thread. | 12-30-2010 |
20110035555 | METHOD AND APPARATUS FOR AFFINITY-GUIDED SPECULATIVE HELPER THREADS IN CHIP MULTIPROCESSORS - Apparatus, system and methods are provided for performing speculative data prefetching in a chip multiprocessor (CMP). Data is prefetched by a helper thread that runs on one core of the CMP while a main program runs concurrently on another core of the CMP. Data prefetched by the helper thread is provided to the helper core. For one embodiment, the data prefetched by the helper thread is pushed to the main core. It may or may not be provided to the helper core as well. A push of prefetched data to the main core may occur during a broadcast of the data to all cores of an affinity group. For at least one other embodiment, the data prefetched by a helper thread is provided, upon request from the main core, to the main core from the helper core's local cache. | 02-10-2011 |
20110067011 | TRANSFORMATION OF SINGLE-THREADED CODE TO SPECULATIVE PRECOMPUTATION ENABLED CODE - In one embodiment a thread management method identifies in a main program a set of instructions that can be dynamically activated as speculative precomputation threads. A wait/sleep operation is performed on the speculative precomputation threads between thread creation and activation, and progress of non-speculative threads is gauged through monitoring a set of global variables, allowing the speculative precomputation threads to determine its relative progress with respect to non-speculative threads. | 03-17-2011 |
20130111194 | METHOD AND SYSTEM TO PROVIDE USER-LEVEL MULTITHREADING | 05-02-2013 |
20130219096 | PROGRAMMABLE EVENT DRIVEN YIELD MECHANISM WHICH MAY ACTIVATE OTHER THREADS - Method, apparatus, and program means for a programmable event driven yield mechanism that may activate other threads. In one embodiment, an apparatus includes execution resources to execute a plurality of instructions and a monitor to detect a condition indicating a low level of progress. The monitor can disrupt processing of a program by transferring to a handler in response to detecting the condition indicating a low level of progress. In another embodiment, thread switch logic may be coupled to a plurality of event monitors which monitor events within the multithreading execution logic. The thread switch logic switches threads based at least partially on a programmable condition of one or more of the performance monitors. | 08-22-2013 |
20150278119 | HARDWARE-ASSISTED VIRTUALIZATION FOR IMPLEMENTING SECURE VIDEO OUTPUT PATH - Systems and methods for employing hardware-assisted virtualization for implementing a secure video output path. An example processing system comprises: a memory; a shared interconnect; and a processing core communicatively coupled to the memory via the shared interconnect, the processing core to: initialize a first virtual machine and a second virtual machine; responsive to receiving a memory access transaction initiated by the first virtual machine to access a memory buffer, tag the memory access transaction with an identifier of the first virtual machine; and responsive to receiving a digital content decoder access transaction initiated by the second virtual machine, tag the digital decoder access transaction with an identifier of the second virtual machine. | 10-01-2015 |