Patent application number | Description | Published |
20090129317 | ACK/NACK DTX detection - In a first aspect of the invention there is a method, apparatus, and executable software product for receiving scheduling information, determining that at least one downlink allocation of the scheduling information was not received, sending a reply to the received scheduling that comprises an indication of discontinuous transmission in response to the determining. In another aspect of the invention there is a method an apparatus to send scheduling information, and receive a reply to the scheduling information comprising an indication of discontinuous transmission that at least one downlink allocation of the scheduling information was not received. | 05-21-2009 |
20090323617 | METHOD AND APPARATUS FOR PROVIDING ACKNOWLEDGMENT BUNDLING - An approach is provided for acknowledgement bundling. Dynamically scheduling of one or more of subframes per bundling window is performed by reusing an assignment index field (e.g., downlink assignment index (DAI) field). The assignment index field has a value greater than or equal to number of previously assigned subframes within the bundling window. The bundling window defines a group of subframes for common acknowledgement. | 12-31-2009 |
20100104047 | MULTIPLE-ANTENNA SPACE MULTIPLEXING SYSTEM USING ENHANCEMENT SIGNAL DETECTION - The multiple-antenna space multiplexing system using enhancement signal detection comprising: a code modulation module for coding and modulating bit information; a signal transmission module for transmitting the modulated signals; a signal reception module for receiving the signals; a signal form transform module for transforming form of a channel matrix H and the received signal vector r; a signal detection module for detecting the received signals; a signal reconstruction module for reconstructing the detection results of in the signal detection module, and obtaining a detected signal; a demodulation decoding module for demodulating and decoding the output of the signal reconstruction module, and outputting bit information. Compared with the conventional detection methods, the system performance is improved in considering the realization complexity. | 04-29-2010 |
20100214972 | METHODS AND APPARATUSES FOR TRANSMITTING DOWNLINK CONTROL SIGNALING ON WIRELESS RELAY LINK - In accordance with an example embodiment of the present invention, a method comprises allocating a control channel resource in a wireless relay transmission frame on a wireless relay link; generating a control signaling based on at least one of a resource allocation scheme, a status of the wireless relay link and a traffic condition of the wireless relay link; mapping the control signaling to the allocated control channel resource via at least one of a time-first mapping, a frequency-first mapping, and a multiplexing mapping; and transmitting the control signaling in the allocated control channel resource on the wireless relay link to at least one associated relay node. | 08-26-2010 |
20100303035 | Multiple Uplink Control Channel Transmission With Reduced Cubic Metric - It is determined that there are X uplink control channel resources available for uplink signaling. Each of those X uplink control channel resources are sub-channelized into a plurality of sub-channels that each defines a unique time instant or point in time. For each of Y units of control information there is selected a unique combination of one of the sub-channels and a modulation (X and Y are each integers greater than one). The Y units of control information are sent on the X uplink control channel resources according to the respectively selected combinations. By example the uplink resources may be an ACK/NAK/DTX bit on a PUCCH. In one example the sub-channels are individual slots of a PUCCH. In another example the sub-channels are the reference-signal part and the data part of a single PUCCH slot. | 12-02-2010 |
20110002276 | System and Methods for ACK/NAK Feedback in TDD Communications - Systems and methods for providing an efficient mechanism for transmitting encoded downlink assignment index (DAI) and for signaling the ACK/NAK information corresponding to downlink grant allocations in an over the air radio telecommunications network with time division duplex (TDD) capability, where aggregation of component carriers (CCs) is used. Downlink control messages containing encoded DAI information are transmitted with downlink allocation grants. A receiver observes the encoded DAI and the downlink allocation grants and forms corresponding ACK/NAK signals. Method embodiments for forming the ACK/NAK signals for CC groups and frames or subframes are provided. The ACK/NAK signals are then encoded using method embodiments and transmitted over parallel channels for each CC group to the transmitter. By using method embodiments for selecting resources for use in the transmission, the last observed DL grant can be identified by the transmitter and the transmitter can detect an error at the receiver. | 01-06-2011 |
20110141878 | ACK/NACK TRANSMISSION ON PUCCH IN LTE-ATDD WITH NXPDCCH STRUCTURE - Systems and methods are provided for enabling different “bundling” methods for downlink transmissions and provide different interpretations of the acknowledgement/negative-acknowledgement bit. A user equipment is configured so that it commonly acknowledges all downlink transmission time intervals within a bundle so that if one packet is determined to be erroneous, all packets in that bundle will be retransmitted. Additionally, the systems and methods are implemented by allowing an interpretation to be applied to the uplink acknowledgement/negative-acknowledgement field such that the user equipment is able to divide bundled downlink packets into smaller windows in Long Term Evolution (LTE) Release 8 time division duplex (TDD) mode. In LTE Advanced (LTE-A) TDD mode, various embodiments provide bundling within the time domain, within the frequency domain, and within a hybrid time-frequency domain. Furthermore, enhanced channel selection methods are also provided in support of the above-mentioned bundling methods in accordance with various embodiments. | 06-16-2011 |
20110237430 | PROCESS FOR PREPARING CATALYST COMPRISING PALLADIUM SUPPORTED ON CARRIER WITH HIGH DISPERSION - A process for preparing a catalyst comprising palladium supported on a carrier via a layered precursor, comprising the following steps: (1) synthesis of hydrotalcite layered precursor which comprises promoting metal element and aluminium on the surface of the carrier of Al | 09-29-2011 |
20120106569 | Apparatus, Method and Article of Manufacture - There is provided a method including performing frequency domain acknowledgement/negative acknowledgement (ACK/NAK) bundling across component carriers within a user equipment reception bandwidth; generating a bundled ACK/NAK value corresponding to at least one code word on the basis of the performed ACK/NAK bundling; and including information relating to the generated bundled ACK/NAK value and the number of detected downlink grants within the user equipment reception bandwidth in an ACK/NAK resource to be transmitted on an uplink control channel. | 05-03-2012 |
20120113913 | Method of Scheduling Data - A method of transmitting uplink control signals/status bits from a user equipment, said user equipment having multiple transmit antennae, and said control signals correspond to a plurality of previous downlink transmissions, wherein said control signals are transmitted over a plurality of PUCCH resources and over said multiple antennae, and transmitted during a single uplink sub-frame. Use of multiple PUCCH resources and multiple antennae allow greater spatial diversity. | 05-10-2012 |
20120120926 | Multiple Uplink Control Channel Transmission with Reduced Cubic Metric - It is determined that there are X uplink control channel resources available for uplink signaling. Each of those X uplink control channel resources are sub-channelized into a plurality of sub-channels that each defines a unique time instant or point in time. For each of Y units of control information there is selected a unique combination of one of the sub-channels and a modulation (X and Y are each integers greater than one). The Y units of control information are sent on the X uplink control channel resources according to the respectively selected combinations. By example the uplink resources may be an ACK/NAK/DTX bit on a of one of the sub-channels and a modulation PUCCH. In one example the sub-channels are individual slots of a PUCCH. In another example the sub-channels are the reference-signal part and the data part of a single PUCCH slot. | 05-17-2012 |
20130021989 | Methods, Apparatuses and Related Computer Program Product for Control Information Signaling - Methods, apparatuses and related computer program product for control information signaling. It is disclosed a method/apparatus comprising predetermining, specifically for each of a plurality of terminals, a transmission mode in correspondence with a predetermined second control information format, transmitting, in a first predetermined portion of a set of control channel candidates, a first control information format of a first size, defining, based on the second control information format, a scheduling grant format of a second size different from the first size to be applied on a second predetermined portion of the set of control channel candidates, equating the first size so as to match with the second size, and transmitting, in the second predetermined portion, the equated first control information; and a method/apparatus comprising monitoring, in the first and second predetermined portions, reception of the first control information format, upon reception of a configuration message relating to the transmission mode, continuing the monitoring and monitoring reception of the scheduling grant format. | 01-24-2013 |
20130039327 | APERIODIC CQI/PMI REQUEST IN CARRIER AGGREGATION - A user's downlink component carriers DL-CCs are divided into groups. An aperiodic CQI/PMI report is triggered by signaling (for example one bit). There is a pattern that maps the signaled trigger to a particular DL-CC within a group of DL-CCs that are configured for a user equipment UE, and that mapped particular DL-CC is determined to be the subject of the aperiodic report. In various embodiments the pattern is implicit and points to the DL-CC for which an aperiodic report has not been sent for more than a threshold time interval; or to the DL-CC for which resources have not been allocated for a periodic report; or to every DL-CC in the group that are activated for the user equipment. Examples are detailed for apparatus, method and computer program from the perspective of the network and from the perspective of the UE. | 02-14-2013 |
20130064209 | Support of UL ACK/NACK Feedback for Carrier Aggregation During Timing Uncertainty Component Carrier (Re-) Configuration/Activation/De-activation Period - An apparatus and a method is described, by which a component carrier configuration, re-configuration, activation or deactivation is performed. In particular, a signaling format used for acknowledgment/negative acknowledgement messages on an uplink control channel is detected, and a codebook size of the acknowledgment/negative acknowledgement messages is decided based on the detected signaling format. | 03-14-2013 |
20130182619 | Enhanced Physical Uplink Control Channel Format Resource Allocation for Time Division Duplex Mode - In one aspect thereof the exemplary embodiments provide a method that includes, when in a time division duplex mode of operation with a user equipment, allocating physical uplink control channel resources by reserving physical uplink control channel resources with a granularity of one acknowledge/negative acknowledge (ACK/NACK) bundle; and sending an indication of the allocated physical uplink control channel resources from a network access node to the user equipment. | 07-18-2013 |
20130256129 | PLASMA PROCESSING APPARATUS - A plasma processing apparatus includes a chamber ( | 10-03-2013 |
20140301280 | METHOD AND APPARATUS FOR PROVIDING ACKNOWLEDGEMENT BUNDLING - An approach is provided for acknowledgement bundling. Dynamically scheduling of one or more of subframes per bundling window is performed by reusing an assignment index field (e.g., downlink assignment index (DAI) field). The assignment index field has a value greater than or equal to number of previously assigned subframes within the bundling window. The bundling window defines a group of subframes for common acknowledgement. | 10-09-2014 |
20140314269 | DEVICE, SYSTEM AND METHOD FOR RECOGNIZING ACTION OF DETECTED SUBJECT - The present disclosure discloses a device, a system and a method for recognizing the action of a detected subject. The device includes an input section for the user to input scene mode selected among a plurality of scene modes; a detection section for detecting the action of the detected subject and outputting an action signal when the device is disposed on the subject; and a microprocessor for processing the action signal according to the selected scene mode, to recognize and output the action of the detected subject in different scene modes. The system includes a device and a terminal, wherein the device is used to recognize the action of the detected subject based on a scene mode selected through the terminal by a user; and the terminal is used to display the action recognition result. The method includes recognizing the action based on a scene mode selected by a user. | 10-23-2014 |
20150049676 | Configuration Uncertainty - For an initial period after informing a user equipment of a change in the number of carriers configured for transmissions from a transmitting device to the user equipment from a first carrier set to a second carrier set, wherein at least one of the first and second carrier sets contains a plurality of carriers: refraining from scheduling data transmissions to said user equipment on one or more carriers other than those common to both said first and second carrier sets; and decoding feedback information received from said user equipment using a number of code basis sequences according to the number of carriers common to both said first and second carrier sets. | 02-19-2015 |
Patent application number | Description | Published |
20100166131 | Method and apparatus for detecting clock frequency deviation - The embodiment of the present disclosure discloses a method and apparatus for detecting frequency deviation of a clock. The method includes: counting the clock to be detected to acquire current counting information; filtering the current counting information to acquire filtered data; and acquiring the frequency deviation of the clock to be detected from the filtered data. According to the embodiments of the present disclosure, the detection accuracy of frequency deviation is improved by filtering the counting information acquired by counting the clock to be detected, and appropriately increasing an amount of information after the filtering, so as to perceive the occurrence of any abnormal dithering, and avoid neglecting of any abnormal condition in periodic or aperiodic queries. | 07-01-2010 |
20120112715 | SNUBBER CIRCUIT FOR BUCK CONVERTER - A snubber circuit for decreasing a voltage spike of a buck converter includes a resistor unit, a capacitor unit, a detecting unit, and a control unit. The resistor unit provides multiple groups of resistance values. The capacitor unit provides multiple groups of capacitance values. The detecting unit detects voltage spikes of the buck converter corresponding to each group of resistance values and capacitance values. The control unit selects each group of resistance and capacitance to respectively connect to the buck converter and determines a group of resistance and capacitance corresponding to a lowest voltage spike by comparing the detected voltage spikes with each other. | 05-10-2012 |
20120146615 | OUTPUT VOLTAGE ADJUSTMENT CIRCUIT FOR BUCK CIRCUITS - An output voltage adjustment circuit for buck circuits includes a microcontroller, first to eighth keys, and a display unit. The first to eighth keys input voltage adjustment signals to the microcontroller. A first input pin of the microcontroller is connected to a voltage output terminal. A second resistor is connected between the first input pin of the microcontroller and ground. A first to a sixth input/output pin of the microcontroller are connected to the display unit. A first to an eighth output pin of the microcontroller are connected to a pulse width modulation (PWM) controller. The first to eighth keys are selectively activated to provide voltage adjustment signals to the microcontroller, sampling output voltages of the voltage output terminal, comparing with a predetermined voltage, controlling the PWM controller to fine tune the duty cycle to output a stable voltage from the voltage output terminal. The display unit displays the voltages on the voltage output terminal. | 06-14-2012 |
20120159227 | POWER DETECTION DEVICE FOR MOTHERBOARD - A motherboard detection device for a motherboard having a plurality of power input terminals. The power detection device includes a current sampling module, a voltage sampling module, a processor, and a display unit. The current sampling module is connected to the power input terminals for obtaining the current of each power input terminal. The voltage sampling module is connected to the power input terminals for obtaining the voltage of each power input terminal. The processor is connected to the current sampling module and the voltage sampling module for acquiring the current and the voltage of each power input terminal and calculating the input power of each power input terminal based on the current and the voltage of each power input terminal to obtain input power data. The display unit is connected to the processor for receiving the input power data from the processor and displaying the input power data. | 06-21-2012 |
20120169312 | DRIVING VOLTAGE ADJUSTING CIRCUIT - A driving voltage adjusting circuit includes a digital rheostat, a control chip, a low dropout regulating circuit, and a driving circuit. The control chip is connected with the digital rheostat, and configured for adjusting the resistance of the digital rheostat. The low dropout regulating circuit is connected with the digital rheostat and outputs an output voltage according to the resistance of the digital rheostat. The driving circuit comprising a number of switch elements connected with each other and a driver configured for driving the switch elements, each of the switch elements comprising a first terminal, a second terminal, and a control terminal configured for controlling connection and disconnection of the first terminal and the second terminal; the first terminal and the second terminal connected with the control chip, the driver is connected with the low dropout regulating circuit and output an driving voltage to the control terminal. | 07-05-2012 |
20120176142 | TEST CIRCUIT FOR RESISTOR CAPACITOR CIRCUITS - An RC test circuit includes an RC circuit, a digital rheostat, a control chip, and an oscillograph. The RC circuit includes a plurality of positive terminals and a plurality of negative terminals. The digital rheostat includes a plurality of rheostats each including a sliding terminal and a fixed terminal. The sliding terminals are correspondingly connected to the positive terminals while the fixed terminals are correspondingly connected to the negative terminals. The control chip is connected to the digital rheostat, and configured for controlling the digital rheostat to change the resistance of each rheostat. The oscillograph is connected to the RC circuit for displaying a waveform of the RC circuit. | 07-12-2012 |
20120179930 | MOTHERBOARD HAVING TIME DELAY CIRCUIT FOR DELAYING PSON SIGNAL - A motherboard includes a motherboard power supply connector and a time delay circuit. The motherboard power supply connector connects a power supply unit. The motherboard power supply connector has a power supply on pin and a power good pin. The power good pin is configured for receiving a power good signal from the power supply unit. The time delay circuit has an input terminal and an output terminal. The input terminal is configured for receiving a power supply on signal. The output terminal is connected to the power supply on pin and is configured for sending the power supply on signal to the power supply on pin after a time delay determined by the time delay circuit. | 07-12-2012 |
20120242306 | DRIVING CIRCUIT - A driving circuit includes a switching circuit, an acquiring circuit, an amplifying circuit, and an adjusting circuit. The switching circuit includes a driving chip and a switching unit. The switching unit is connected between a power source and a load, the driving chip is configured for controlling the connection and disconnection of the switching unit. The acquiring circuit is connected between the switching unit and the load, and is configured for providing a feedback to the amplifying circuit. The amplifying circuit includes two amplifying input terminals connected to two terminals of the acquiring circuit and an amplifying output terminal outputting an amplified voltage. The adjusting circuit is connected to the amplifying output terminal and is configured for outputting different control voltages to the driving chip according to the amplified voltage. The driving chip outputs different driving voltages to the switching unit according to the control voltages. | 09-27-2012 |
20130241506 | POWER CONTROL CIRCUIT AND LOOP ANALYZING APPARATUS COMPRISING SAME - A power supply control circuit includes a main controller, a current detection unit electronically connected to the main controller, and a mode switch unit electronically connected to the main controller. The current detection unit cooperates with the main controller in detecting a value of an output current of a power supply circuit. The main controller determines whether the power supply circuit is operating in a discontinuous conduction mode or in a continuous conduction mode according to the value of the output current of the power supply circuit, and controls the mode switch unit to switch the power supply circuit to the continuous conduction mode when the power supply circuit operates in the discontinuous conduction mode. | 09-19-2013 |
20130271165 | OUTPUT IMPEDANCE TESTING DEVICE - A device that tests an output impedance of a voltage regulator module (VRM) includes a controller, a current regulating circuit, a voltage sampling circuit, and a current sampling circuit. The voltage sampling circuit samples an instantaneous alternating output voltage of the VRM, and outputs the instantaneous alternating output voltage to the controller. The current sampling circuit cooperates with the controller in sampling the instantaneous output current of the VRM. The controller controls the current regulating circuit to regulate the instantaneous output current of the VRM until the instantaneous alternating output voltage is about equal to a predetermined reference voltage, and calculates an output impedance of the VRM according to the instantaneous alternating output voltage and instantaneous output current when the instantaneous alternating output voltage is about equal to the predetermined reference voltage. | 10-17-2013 |
20130328405 | GROUND TEST CIRCUIT - A ground test circuit for a power supply unit includes a sampling circuit, a converting circuit, a processing circuit, and a switch circuit. The sampling circuit detects a voltage difference between a first ground terminal and a second ground terminal. The converting circuit converts the voltage difference to a digital value. The processing circuit compares the digital value to a predetermined value. As long as the digital value is smaller than the predetermined value, the switch circuit allows an external power source to be connected to the power supply unit. Thereby, the ground test circuit controls the connection between the external power source and the power supply unit according to the result of comparison of values done by the processing circuit. | 12-12-2013 |
20140028331 | INDUCTANCE MEASUREMENT CIRCUIT - An inductance measurement circuit includes a control circuit, a constant current supply circuit, a voltage detecting circuit, and a display circuit. The control circuit controls the constant current supply circuit to supply a first current for a first inductor. The control circuit controls the voltage detecting circuit to detect a voltage on the first inductor. The control circuit obtains an internal resistance of the first inductor by dividing the first voltage by the first constant current. The display circuit displays the internal resistance of the first inductor. | 01-30-2014 |
20140140074 | Light-Emitting Device - A light-emitting device, comprising: a cover ( | 05-22-2014 |
20140160726 | LIGHTING DEVICE - A lighting device may include a circuit board, at least one LED lighting chip provided on one side of the circuit board, and a phosphor layer arranged to enclose the LED lighting chip, wherein the phosphor layer has different thicknesses at different light emergence angles. | 06-12-2014 |
20140186131 | HOLDING WRENCH - A holding wrench includes a clamping assembly and a pair of handles. The clamping assembly includes a housing, a transmission gear, a first latching member, a second latching member, and an adjusting subassembly. The first latching member and the second latching member engage with the transmission gear. The adjusting subassembly includes an adjusting member, a pair of pushing members protruding from the adjusting member, and a pair of resisting members. The adjusting member defines a pair of latching grooves. The pair of pushing members is located between the first latching member and the second latching member. When the adjusting member is moved toward the second latching member, one of the pair of pushing member pushes the second latching member away from the transmission gear, and the pair of resisting members latches into the pair of latching grooves, thereby positioning the adjusting member. | 07-03-2014 |
20140233211 | LED LUMINAIRES BASED ON COLOR MIXING AND REMOTE PHOSPHOR ARRANGEMENT - In various embodiments, a luminaire may include: two or more groups of light emitting elements, each group of light emitting elements having respective wavelength range; and a fluorescence component being capable of generating fluorescence under excitation of the light emitted from said light emitting elements, wherein said fluorescence component is spaced apart from said light emitting elements in a light propagation direction of said light emitting elements, and the light of each group of said light emitting elements is combined with said fluorescence into white light. | 08-21-2014 |
20140233230 | LED LUMINARY AND METHOD FOR FABRICATING THE SAME - In various embodiments, an LED luminary may include: a plurality of LED light emitting elements; and an installation component for installing the plurality of LED light emitting elements in the LED luminary, wherein the plurality of LED light emitting elements are installed so that the LED light emitting elements are not on the same plane. In various embodiments, a method for fabricating an LED luminary may include: preparing an installation component; and installing a plurality of LED light emitting elements in the LED luminary through the installation component so that the LED light emitting elements are not on the same plane. | 08-21-2014 |
20140281596 | FREQUENCY ADJUSTMENT SYSTEM AND METHOD - A frequency adjustment system includes a phase-locked loop (PLL) circuit, an adjusting circuit, and a voltage regulator module (VRM). The PLL circuit outputs a trigger signal when a communication frequency of a chip changes. The adjusting circuit adjusts a clock frequency of the adjusting circuit to receive communication data. The adjusting circuit further outputs a control signal to the VRM. The VRM outputs a voltage according to the control signal. | 09-18-2014 |
20140362590 | ELECTRONIC MODULE, LIGHTING DEVICE AND MANUFACTURING METHOD OF THE ELECTRONIC MODULE - An electronic module to be mounted on a mounting surface may include: a circuit board provided with a heat source, wherein a thermal via is formed through the circuit board and is in thermal contact with the heat source; and a potting material packaging the circuit board at least at the other side opposite to one side of heat source, wherein the potting material has a recess formed in at least part of an area corresponding to the thermal via at the other side of the circuit board and a thermal conductive material, which is thermal-conductively connected to the mounting surface, is filled in the recess. | 12-11-2014 |
Patent application number | Description | Published |
20090049352 | CONTROL APPARATUS AND METHOD FOR CONTROLLING MEASURING DEVICES TO TEST ELECTRONIC APPARATUSES - An electronic apparatus testing method is provided. The method includes the step of: reading a product ID of the electronic apparatus when the electronic apparatus is connected to a control apparatus; determining the device type ID from the product ID, wherein the product ID comprises basic information of the electronic apparatus, determining the script files of the functions of the electronic apparatus in the testing table according to the device type ID; obtaining the script files from a data storage and running the script files to test functions of the electronic apparatuses, sending a control instruction to the corresponding measuring device of the function to control the measuring device test the function during the process of running the script files; and displaying test results through a display of the control apparatus. | 02-19-2009 |
20090052678 | AUDIO TEST APPARATUS AND TEST METHOD THEREOF - An audio test apparatus, and an exemplary audio test method that includes: processing an audio file through two independent channels; outputting no signals from a left channel and from a right channel in a first time period; receiving noise signals from the left and right channels; outputting single-frequency signals from the left channel only in a second time period; receiving the single-frequency signals from the left channel and crosstalk signals from the right channel; outputting multi-frequency signals from the left and right channels in a third time period; receiving the multi-frequency signals from the left and right channels; outputting single-frequency signals from the right channel only in a fourth time period; receiving the crosstalk signals from the left channel and the single-frequency signals from the right channel; and testing parameters according to the signals received during the four time periods. | 02-26-2009 |
20120126767 | BUCK CONVERTER - A buck converter includes a first electrical switch and a second electrical switch connected in series, a PWM module coupled to the gate of the first electrical switch through a first adjustable resistance module and coupled to the gate of the second electrical switch through a second adjustable resistance module, a filter circuit coupled between the connecting node of the two different electrical switches and an output node, and a control module for adjusting values of the first adjustable resistance module and the second adjustable resistance module and acquiring a voltage value from the connecting node. | 05-24-2012 |
20120133349 | MEASUREMENT CIRCUIT FOR BUCK CIRCUIT - A measurement circuit for overload protection is applied in a buck circuit. The buck circuit includes a pulse width modulation (PWM) controller and a voltage output terminal. The measurement circuit includes a resistance setting circuit to connect different resistances to the PWM controller of the buck circuit. A switch circuit turns the measurement circuit on or off. A current collection circuit receives a voltage from the voltage output terminal of the buck circuit and transforms the received voltage to a current, and amplifies the transformed current and outputs the amplified current to the resistance setting circuit. The resistance setting circuit chooses a resistance through comparison of the amplified current with a preset current. A display unit displays the chosen resistance. | 05-31-2012 |
20120161729 | BUCK CONVERTER - A buck converter includes an input unit, an inductor, and a filter capacitor. The input unit has an input node connected to a power source and an intermediate node connected to an output node through the inductor. The filter capacitor is coupled between the output node and ground. A first RC integral circuit is in parallel connection with the first inductor, a voltage acquired unit is in parallel connection with the capacitor of the RC integral circuit for obtaining a voltage U | 06-28-2012 |
20120161781 | MEASUREMENT CIRCUIT FOR CAPACITOR - A measurement circuit includes a switch unit with a number of keys selectively pressed to output different resistance regulating signals. A resistance setting circuit receives the resistance regulating signals and connects different resistances to a voltage circuit and a current circuit. The voltage circuit outputs different voltages. The current voltage receives a voltage from the voltage circuit and outputs a current to a capacitor. A detecting circuit measures a temperature of the capacitor and outputs the temperature to the resistance setting circuit. The resistance setting circuit compares the received temperature with a preset temperature. If the received temperature is equal to or greater than the preset temperature, the resistance setting circuit outputs short-circuit information of the capacitor. If the received temperature is less than the preset temperature, the resistance setting circuit outputs normal information of the capacitor. A display unit displays the information of the capacitor. | 06-28-2012 |
20120161798 | MEASUREMENT CIRCUIT FOR POWER SUPPLY - A measurement circuit includes a switch unit with a number of keys selectively pressed to output different resistance regulating signals. A resistance setting circuit receives the resistance regulating signals and connects different resistances to a control circuit. The control circuit obtains a voltage according to the chosen resistance by the resistance setting circuit and compares the voltage with a preset voltage. If the voltage is greater than the preset voltage, the control circuit outputs a high level signal to a control pin of a pulse width modulation (PWM) controller, to control a voltage unit to output a voltage. If the voltage is less than the preset voltage, the control circuit outputs a low level signal to the control pin of the PWM controller, to control the voltage unit to not output a voltage. A display unit displays the chosen resistance. | 06-28-2012 |
20120169314 | BUCK CONVERTER - A buck converter includes a first MOSFET and a second MOSFET connected in series, a PWM module coupled to gates of the first MOSFET and the second MOSFET, and a control unit being coupled to the input current acquired unit, the input voltage acquired unit, the output current acquired unit, the output voltage acquired unit and the PWM module respectively, wherein the control unit controls a switch frequency of the PWM module and acquires the input current, the input voltage, the output current and the output voltage from the input current acquired unit, the input voltage acquired unit, the output current acquired unit and the output voltage acquired unit respectively. | 07-05-2012 |
20120169321 | MEASURING DEVICE FOR HARD DISK DRIVE - A measuring device for a hard disk drive includes a first input node, a hard disk drive having a first input terminal, the first input terminal being coupled to the first input node to provide power to the hard disk drive. A first input current sampling unit is coupled between the first input node and the first input terminal of the hard disk drive to obtain a first input current Iin1. A first input voltage sampling unit is coupled to the first input terminal of the hard disk drive to obtain a first input voltage Uin1. A control unit is coupled to the first input current sampling unit and the first input voltage sampling unit to receive the first input current and the first input voltage. | 07-05-2012 |
20120176166 | DRIVER CIRCUIT - A driver circuit drives a pulse width modulation (PWM) controller. The driver circuit includes an enabling circuit, a power supply input control circuit, a stabilizing circuit, and a discharge circuit. The stabilizing circuit is electrically connected to the PWM controller. The power supply input control circuit is electrically connected between the enabling circuit and the stabilizing circuit. The discharge circuit is electrically connected between the stabilizing circuit and the ground. In response to the driver circuit working in normal operation, the enabling circuit enables the power supply input control circuit to output a working voltage to the stabilizing circuit, and in response to the process of the driver circuit restarting, the enabling circuit enables the power supply input to stop outputting power supply to the stabilizing circuit. The discharge circuit leads a residual voltage of the stabilizing circuit to the ground, during the process of the driver circuit being restarted. | 07-12-2012 |
20120176715 | RESISTANCE DETERMINING SYSTEM FOR OVER VOLTAGE PROTECTION CIRCUIT - A resistance determining system for an over voltage protection (OVP) circuit, includes an external power source, a microcontroller, a digital rheostat and a display unit. The external power source supplies an external voltage to the OVP circuit. The microcontroller stores an over voltage value. The microcontroller is connected to the external power source and configured to detect the external voltage and compare the external voltage with the over voltage value. The digital rheostat is connected to the microcontroller and includes a first rheostat having two connection terminals respectively connected to two first connection ends of the OVP circuit. The microcontroller adjusts the first rheostat to be a first resistance value to activate the OVP circuit when the external voltage is substantially equal to the over voltage value. The display unit is connected to the microcontroller and configured to display the first resistance value. | 07-12-2012 |
20120182660 | RESISTANCE DETERMINING SYSTEM AND METHOD FOR CIRCUIT PROTECTION - A resistance determining system and method for a protection circuit, includes a resistance determining unit. The resistance determining unit interconnects a microcontroller and a digital resistor, where the microcontroller has first setting voltage corresponding to a first voltage threshold for activating the protection circuit, and the microcontroller is capable of receiving and converting a first external voltage input to the protection circuit to be a first converted voltage. The digital resistor includes a first variable resistor having two terminals connected to the respective first terminal and the second terminal. The microcontroller adjusts a resistance of the first variable resistor to be a first threshold resistance if the first converted voltage is substantially equal to the first voltage threshold, and the first resistance is determined to be substantially equal to the first threshold resistance. | 07-19-2012 |
20120182661 | OVERCURRENT PROTECTION DEVICE - An overcurrent protection device includes a power input terminal, a power output terminal, a first signal terminal, a second signal terminal, a testing circuit, and a switch element. The power input terminal and the first signal terminal are connected to a power supply. The power output terminal and the second signal terminal are connected to a computer motherboard. If the first and second terminals are disconnected from each other when the computer motherboard works, the power supply stops working. The testing circuit includes a fixed resistor and a control chip parallel connected between the power input and output terminal. The control chip stores a predetermined voltage threshold, and detects voltage between the two terminals of the fixed resistor, and compares the measured voltage with the predetermined voltage threshold. The switch element disconnects the first and second signal terminals when the measured voltage is greater than the predetermined voltage threshold. | 07-19-2012 |
20120262195 | RESISTANCE DETERMINING SYSTEM AND METHOD - A resistance determining system is used to determine an offsetting resistance of a mainboard to establish a predetermined offset voltage. The system includes an input equipment, a single-chip, and a resistor. The input equipment sets a predetermined standard voltage of the mainboard. The resistor supplies the mainboard with various resistances, to adjust real output voltage of the mainboard. The single-chip monitors the real output voltage of the mainboard, and adjusts the resistance of the resistor until the difference between the real output voltage and the predetermined standard voltage is equal to a predetermined offset voltage. | 10-18-2012 |
20120267954 | LOAD LINE CALIBRATION DEVICE - An adjusting device adjusts a load line of a CPU power supply circuit. The adjusting device includes a controller, a DC electronic load device, a voltage follower, an adjustable resistor, and an indicator. The controller controls the DC electronic load device to change an output current of the circuit. The voltage follower sends an output voltage of the circuit to the controller. The controller calculates the load line of the circuit based on the output current and the output voltage of the circuit, determines whether the load line satisfies the required value, changes a resistance of the adjustable resistor until the load line satisfies the required value, and sends a resistance of the adjustable resistor to the indicator. | 10-25-2012 |
20120306273 | SEQUENCE CONTROL CIRCUIT FOR POWER SOURCE - A sequence control circuit for power sources includes two switched circuits and a sequence control unit. Each of the switched circuits has a control node and is coupled between a power source and a load. The sequence control unit includes two output terminals coupled to the control nodes. The output terminals generate control signals to control the sequence of the circuits being turned on. | 12-06-2012 |
20120311352 | POWER CIRCUIT FOR DATA STORAGE DEVICE - A power circuit which is applicable to a data storage device. A boost circuit receives a first voltage and converts it to a second voltage. A charging and discharging circuit receives the second voltage and charges a charging capacitor. As long as a voltage detecting circuit detects that the second voltage exists, it outputs a first selection signal. When the voltage detecting circuit detects that the second voltage does not exist, it outputs a second selection signal and also outputs a signal to the charging and discharging circuit, to release a stored voltage. A voltage selection circuit will output the second voltage according to the first selection signal, or will output the stored voltage from the charging capacitor according to the second selection signal. Buck circuits convert the second voltage or the stored voltage to the different voltages required by a control chip of the data storage device. | 12-06-2012 |
20120316817 | MEASUREMENT CIRCUIT FOR MEASURING DIRECT CURRENT RESISTANCE OF INDUCTOR - A circuit for measuring the DC resistance of an inductor includes an input unit, a microprocessor module, a current source and a voltage detecting unit. The microprocessor module receives signals from the input unit and generates different signals to command constant currents through the inductor by the current source. The voltage detecting unit reads voltages of the inductor and outputs the voltages obtained to the microprocessor module. According to the currents and the voltages read, the microprocessor module may calculate the DC resistance(s) of the inductor. | 12-13-2012 |
20120326682 | POWER SUPPLY CIRCUIT WITH SPIKE SUPPRESSION CIRCUIT - A power supply circuit includes a pulse width modulation (PWM) chip, a number of phase circuits, a voltage output end, and a spike suppression circuit. The spike suppression circuit is connected to each of the phase circuits and the voltage output end. The PWM chip controls all of the phase circuits to alternately output power supply voltages according to a predetermined sequence. The spike suppression circuit receives the power supply voltages, and filters out voltage spikes in the power supply voltages, thereby outputting steady voltages to the voltage output end. | 12-27-2012 |
20130017735 | COMPUTER MEMORY DEVICEAANM LUO; QI-YANAACI Shenzhen CityAACO CNAAGP LUO; QI-YAN Shenzhen City CNAANM CHEN; PENGAACI Shenzhen CityAACO CNAAGP CHEN; PENG Shenzhen City CNAANM TONG; SONG-LINAACI Shenzhen CityAACO CNAAGP TONG; SONG-LIN Shenzhen City CN - A computer memory device includes a circuit board, a number of chips mounted on a surface of the circuit board, and an edge connector set on a bottom side of the circuit board. The edge connector includes ground pins, power pins, and data pins. Top ends of the ground pins, the power pins, and the data pins are in alignment with one another. Each ground pin is longer than each of the power pins and the data pins. | 01-17-2013 |
20130031280 | DETECTION DEVICE - A detection device to detect a power serving time of a super capacitor for a power-disconnected storage card and an amount of the data packets capable of being stored during the detected serving time is provided. The power-disconnected storage card includes a memory. The detection device includes a power supply unit, the super capacitor, a controller, a storage unit, and a detection unit. The storage unit stores the data packets. The detection unit includes a charge notification module, a data notification module and a time module. The charge notification module generates a first notification signal to the time module. The data notification module generates a second notification signal to the time module when the storage unit transmits the data packet to the memory. The time module records time when the memory completely store the data packet according to the first notification signal and the second notification signal. | 01-31-2013 |
20130091373 | MONITORING DEVICE AND METHOD FOR MONITORING POWER PARAMETERS OF CENTRAL PROCESSING UNIT OF COMPUTING DEVICE - A monitor device is used to monitor power parameters of a CPU of a computing device. The monitoring device comprises a main circuit board, a connector, and a parameter monitoring device. The parameter monitoring device comprises an acquisition unit, a processing unit, and a display unit. The main circuit board is connected to a power supply and provides power signals to one or more power pins of the CPU. The connector is connected between the main circuit board and the CPU. The parameter monitoring device is connected to the CPU through the connector. The acquisition unit acquires a voltage passing through each power pin of the CPU after the CPU is powered to work. The processing unit processes the voltage acquired from each of the one or more power pins to obtain power parameters of the CPU. The display unit displays the power parameters. | 04-11-2013 |
20130091374 | MONITORING DEVICE AND METHOD FOR MONITORING POWER PARAMETERS OF MEMORY BANK OF COMPUTING DEVICE - A monitored device is used to monitor power parameters of a memory bank of a computing device. The monitoring device includes a main circuit board, a connector, and a parameter monitoring device. The parameter monitoring device comprises an acquisition unit, a processing unit, and a display unit. The main circuit board is connected to a power supply and providing power signals to one or more power pins of the memory bank. The connector is connected between the main circuit board and the memory bank. The acquisition unit acquires a voltage passing through each power pin of the memory bank when power is supplied to the memory bank. The processing unit processes the voltage acquired from each of the one or more power pins to obtain power parameters of the memory bank. The display unit displays the power parameters of the memory bank. | 04-11-2013 |
20130116956 | CAPACITANCE MEASUREMENT CIRCUIT - A capacitance measurement circuit includes a charge module to charge a capacitor, a discharge module to hold the capacitor discharge at a constant current, and a control module. The control module includes a timer, a detecting sub-module, a trigger sub-module, and a computing sub-module. The detecting sub-module detects whether the capacitance is fully charged and detects voltages V and discharge current I when the capacitor discharges. The trigger sub-module triggers the charge module to stop charging the capacitor and triggers the timer starts to time a preset discharge time once the capacitor is fully charged. The computing sub-module computes any output voltage differences during the discharge time, and further computes the capacitance value of the capacitor. | 05-09-2013 |
20130124880 | POWER SUPPLY DEVICE FOR CENTRAL PROCESSING UNIT - A power supply device is configured for supplying electrical power to a central processing unit (CPU) of an electronic device. The CPU operates in a number of working modes. The power supply device includes a power supply module operating in a number of power supply modules corresponding to the working modes of the CPU, a number of compensation circuits respectively corresponding to the power supply modes, and a control module. The control module determines the working mode of the CPU and controls the corresponding compensation circuit to electrically connect to the power supply module to provide a loop compensation to the power supply module which improves stability and responding speed of the power supply module. | 05-16-2013 |
20130127447 | ELECTRICAL PARAMETER DETECTION DEVICE FOR PERIPHERAL COMPONENT INTERCONNECT DEVICES - An electrical parameter detection device is configured for detecting electrical parameters of a peripheral component interconnect (PCI) connector including a plurality of power pins. The electrical parameter detection device includes a processor module, a first detection module, and a second detection module. The processor module continuously detects voltage values of electric potentials provided by each of the power pins of the PCI connector using the first detection module, and determines time sequences of the electric potentials according to the voltage values of the electric potentials. Furthermore, the processor module detects the amount of power provided by each of the power pins of the PCI connector using the second detection module. | 05-23-2013 |
20140015542 | MEASUREMENT CIRCUIT FOR LEAKAGE CURRENT OF CAPACITOR - A measurement circuit includes an instruction input unit, a charging circuit to charge a capacitor, a charging and discharging circuit to control the capacitor to leakage discharge, a control circuit, a first amplifying circuit, and a display unit. The control circuit receives a measurement instruction through the instruction input unit to control the charging circuit to charge the capacitor, and receives a stop charging signal from the charging circuit when a voltage of the capacitor reaches a saturation voltage for controlling the charging circuit to stop charging the capacitor. The first amplifying circuit measures a leakage voltage of the capacitor, amplifies the measured leakage voltage, and outputs the amplified leakage voltage to the control circuit. The display unit displays the leakage voltage of the capacitor. | 01-16-2014 |
20140019075 | MEASUREMENT SYSTEM FOR MEASURING INDUCTANCE - A measurement system includes a control circuit, a measurement circuit, and a display circuit. The measurement circuit includes a first capacitor. The control circuit outputs control signals to control first or second inductors and the first capacitor to compose an LC circuit. Inductance can be gained according to the formula: | 01-16-2014 |