Patent application number | Description | Published |
20090249103 | PLATFORM POWER MANAGEMENT BASED ON LATENCY GUIDANCE - Embodiments of a system for receiving power management guidelines from a first plurality of components of a system, and developing a power management policy to manage one or more of a second plurality of components of the system based at least in part on the received power management guidelines. Other embodiments are described. | 10-01-2009 |
20110096048 | DISPLAY BRIGHTNESS ADJUSTMENT - Embodiments of the present invention can receive a data point defining an ambient light level associated with a display and a corresponding brightness adjustment of the display with respect to a reference brightness. The embodiments can then define a brightness response model for the display based on the data point and at least one additional data point. | 04-28-2011 |
20110157198 | Techniques for aligning frame data - Techniques are described that can used to synchronize the start of frames from multiple sources so that when a display is to output a frame to a next source, boundaries of current and next source are aligned. Techniques are useful to avoid visual distortions when changing from a first video source to a second video source. | 06-30-2011 |
20110157202 | Techniques for aligning frame data - Techniques are described that can used to synchronize the start of frames from multiple sources so that when a display is to output a frame to a next source, boundaries of current and next source are aligned. Techniques attempt to avoid visible glitches when switching from displaying a frame from a first source to displaying frames from a second source even though alignment is achieved by switching if frames that are to be displayed from the second source are similar to those displayed from the first source. | 06-30-2011 |
20110264938 | METHOD AND SYSTEM FOR DETERMINING AN ENERGY-EFFICIENT OPERATING POINT OF A PLATFORM - A method and system for determining an energy-efficient operating point of the platform or system. The platform has logic to dynamically manage setting(s) of the processing cores and/or platform components in the platform to achieve maximum system energy efficiency. By using the characteristics of the workload and/or platform to determine the optimum settings of the platform, the logic of the platform facilitates performance guarantees of the platform while minimizing the energy consumption of the processor core and/or platform. The logic of the platform identifies opportunities to run the processing cores at higher performance levels which decreases the execution time of the workload and transitions the platform to a low-power system idle state after the completion of the execution of the workload. Since the execution time of the workload is reduced, the platform spends more time in the low-power system idle state and therefore the overall system energy consumption is reduced. | 10-27-2011 |
20120198248 | PLATFORM POWER MANAGEMENT BASED ON LATENCY GUIDANCE - Embodiments of a system for receiving power management guidelines from a first plurality of components of a system, and developing a power management policy to manage one or more of a second plurality of components of the system based at least in part on the received power management guidelines. Other embodiments are described. | 08-02-2012 |
20120254645 | CONTROL OF PLATFORM POWER CONSUMPTION USING COORDINATION OF PLATFORM POWER MANAGEMENT AND DISPLAY POWER MANAGEMENT - Control of platform control of platform power consumption using selective updating of a display image. An embodiment of an apparatus includes a display controller to transfer pixel data from a frame buffer to a video display and a detection element to track updates to the frame buffer, the detection element to identify a portion of the pixel data that has been changed from a previous image, where the display controller is to provide the video display with the identified portion of the pixel data. | 10-04-2012 |
20130007483 | METHOD AND APPARATUS TO REDUCE IDLE LINK POWER IN A PLATFORM - A method and apparatus to reduce the idle link power in a platform. In one embodiment of the invention, the host and its coupled endpoint(s) in the platform each has a low power idle link state that allows disabling of the high speed link circuitry in both the host and its coupled endpoint(s). This allows the platform to reduce its idle power as both the host and its coupled endpoint(s) are able to turn off their high speed link circuitry in one embodiment of the invention. | 01-03-2013 |
20130007486 | METHOD AND SYSTEM FOR DETERMINING AN ENERGY-EFFICIENT OPERATING POINT OF A PLATFORM - A method and system for determining an energy-efficient operating point of the platform or system. The platform has logic to dynamically manage setting(s) of the processing cores and/or platform components in the platform to achieve maximum system energy efficiency. By using the characteristics of the workload and/or platform to determine the optimum settings of the platform, the logic of the platform facilitates performance guarantees of the platform while minimizing the energy consumption of the processor core and/or platform. The logic of the platform identifies opportunities to run the processing cores at higher performance levels which decreases the execution time of the workload and transitions the platform to a low-power system idle state after the completion of the execution of the workload. Since the execution time of the workload is reduced, the platform spends more time in the low-power system idle state and therefore the overall system energy consumption is reduced. | 01-03-2013 |
20130275737 | COLLABORATIVE PROCESSOR AND SYSTEM PERFORMANCE AND POWER MANAGEMENT - The present invention relates to a platform power management scheme. In some embodiments, a platform provides a relative performance scale using one or more parameters to be requested by an OSPM system. | 10-17-2013 |
20130275796 | COLLABORATIVE PROCESSOR AND SYSTEM PERFORMANCE AND POWER MANAGEMENT - The present invention relates to a platform power management scheme. In some embodiments, a platform provides a relative performance scale using one or more parameters to be requested by an OSPM system. | 10-17-2013 |
20130283032 | COLLABORATIVE PROCESSOR AND SYSTEM PERFORMANCE AND POWER MANAGEMENT - The present invention relates to a platform power management scheme. In some embodiments, a platform provides a relative performance scale using one or more parameters to be requested by an OSPM system. | 10-24-2013 |
20140132616 | HYBRID DISPLAY FRAME BUFFER FOR DISPLAY SUBSYSTEM - A hybrid display frame buffer for a display subsystem. An embodiment of an apparatus a first logic to split a video image into a first data portion and a second data portion; a display frame buffer including a first memory component having a first type of memory and a second memory component having a second type of memory, the first logic to write the first data portion to the first memory component and the second data portion to the second memory component; and a second logic to read the first data portion from the first memory component and the second data component from the second memory component, and to combine the first data portion and the second data portion to generate a combined video image. | 05-15-2014 |
20140168241 | TECHNIQUES FOR MANAGING SYSTEM POWER USING DEFERRED GRAPHICS RENDERING - An apparatus may include a memory to store one or more graphics rendering commands in a queue after generation. The apparatus may also include a processor circuit, and a graphics rendering command manager for execution on the processor to dynamically determine at one or more instances a total execution duration for the one or more graphics rendering commands, where the total execution duration comprises a total time to render the one or more graphics rendering commands. The graphics rendering command manager also may be for execution on the processor to generate a signal to transmit the one or more graphics rendering commands for rendering by a graphics processor when the total execution duration exceeds a graphics rendering command execution window. | 06-19-2014 |
20140189385 | INTELLIGENT RECEIVE BUFFER MANAGEMENT TO OPTIMIZE IDLE STATE RESIDENCY - Methods and systems may provide for determining a plurality of buffer-related settings for a corresponding plurality of idle states and outputting the plurality of buffer-related settings to a device on a platform. The device may determine an observed bandwidth for a channel associated with a receive buffer and identify a selection of a buffer-related setting from the plurality of buffer-related settings based at least in part on the observed bandwidth. In one example, each buffer-related setting includes a latency tolerance and a corresponding idle duration. | 07-03-2014 |
20140189398 | TECHNIQUES FOR PLATFORM DUTY CYCLING - Various embodiments are generally directed to an apparatus, method and other techniques for detecting active and semi-active workloads during execution on a platform processing device and enabling a duty cycle process to reduce thermal output and power consumption, and align unaligned activity. In various embodiments, the duty cycle processing may be enabled during an active workload when thermal output or power consumption is above a thermal threshold or power consumption threshold that is below an efficient operating point for the platform processing device. The duty cycle processing may also be enabled during semi-active workloads when the workload causes the platform processing device to be underutilized and unaligned. The duty cycle processing may comprise enabling a forced idle period for the platform processing device. Other embodiments are described and claimed. | 07-03-2014 |
20140189403 | PERIODIC ACTIVITY ALIGNMENT - Methods and systems may provide for determining a latency constraint associated with a platform and determine an idle window based on the latency constraint. In addition, a plurality of devices on the platform may be instructed to cease one or more activities during the idle window. In one example, the platform is placed in a sleep state during the idle window. | 07-03-2014 |
20140189694 | MANAGING PERFORMANCE POLICIES BASED ON WORKLOAD SCALABILITY - Methods and systems may provide for identifying a workload associated with a platform and determining a scalability of the workload. Additionally, a performance policy of the platform may be managed based at least in part on the scalability of the workload. In one example, determining the scalability includes determining a ratio of productive cycles to actual cycles. | 07-03-2014 |
20140267336 | DATA TRANSMISSION FOR DISPLAY PARTIAL UPDATE - Data transmission for display partial update. An embodiment of an apparatus includes a display controller to transfer pixel data from a frame buffer to a video display and to select a granularity of a plurality of granularities for units of data for the transfer of the pixel data, and a detection element to track updates to the frame buffer, the detection element to identify at least a first damage area of the pixel data that has been changed from a previous image, wherein the display controller is to provide the video display with the identified first damage area of the pixel data in more or more units of data of the chosen granularity. | 09-18-2014 |
20140310543 | METHOD AND APPARATUS TO REDUCE IDLE LINK POWER IN A PLATFORM - A method and apparatus to reduce the idle link power in a platform. In one embodiment of the invention, the host and its coupled endpoint(s) in the platform each has a low power idle link state that allows disabling of the high speed link circuitry in both the host and its coupled endpoint(s). This allows the platform to reduce its idle power as both the host and its coupled endpoint(s) are able to turn off their high speed link circuitry in one embodiment of the invention. | 10-16-2014 |
20140310550 | PCIE DEVICE POWER STATE CONTROL - An apparatus, system, and method, the method including receiving an indication of a idle state capability of a platform connected device; determining, by a chipset, an idle power state compatible with the device; and directing the device to enter the determined idle power state based on a power state of the chipset. | 10-16-2014 |