Patent application number | Description | Published |
20090184697 | SYSTEM, APPARATUS, AND METHOD FOR SELECTABLE VOLTAGE REGULATION - Apparatuses, systems, and methods are disclosed for generating, regulating, and modifying various voltage levels on a semiconductor device using a current mirroring digital-to-analog voltage regulator. The voltage regulator operates by mirroring a reference current onto a selectable current level and controlling the selectable current level with a digital input to a plurality of switched CMOS devices connected in parallel. The switched CMOS devices generate the selectable current level responsive to the digital input and proportional to the reference current. The selectable current level is combined with an output of a voltage divider to generate a monitor signal. The monitor signal is compared to a reference voltage and the results of the comparison controls a charge pump to generate a pumped voltage. The pumped voltage is fed back to the voltage divider, which includes a feedback resistor and a reference resistor connected in series between the pumped voltage and ground. | 07-23-2009 |
20120257457 | METHOD AND APPARATUS FOR PRE-CHARGING DATA LINES IN A MEMORY CELL ARRAY - Memories, pre-charge circuits, and methods for pre-charging memory are described. One such method includes providing a voltage to a data line and adjusting the voltage provided to the data line based at least in part on a voltage difference between a target voltage and a voltage of the data line being pre-charged. An example pre-charge circuit includes a voltage generator configured to generate an output voltage having a magnitude based at least in part on a reference voltage and a feedback signal, first and second drivers, and a voltage detector. The voltage detector is configured to determine a voltage difference between the reference voltage and a sample voltage of a data line coupled to the second driver and generate the feedback signal based at least in part on the difference. | 10-11-2012 |
20130107623 | MEMORY CELL SENSING | 05-02-2013 |
20130155780 | APPARATUSES AND METHODS FOR COMPARING A CURRENT REPRESENTATIVE OF A NUMBER OF FAILING MEMORY CELLS - Apparatuses and methods for comparing a sense current representative of a number of failing memory cells of a group of memory cells and a reference current representative of a reference number of failing memory cells is provided. One such apparatus includes a comparator configured to receive the sense current and to receive the reference current. The comparator includes a sense current buffer configured to buffer the sense current and the comparator is further configured to provide an output signal having a logic level indicative of a result of the comparison. | 06-20-2013 |
20150213848 | METHODS AND APPARATUSES FOR PROVIDING A PROGRAM VOLTAGE RESPONSIVE TO A VOLTAGE DETERMINATION - Apparatuses and methods for providing a program voltage responsive to a voltage determination are described. An example apparatus includes a memory array comprising a plurality of access lines. The example apparatus further includes a memory access circuit coupled to the memory array. The memory access circuit is configured to, during a memory program operation, provide an inhibit voltage to the plurality of access lines. The memory access circuit is further configured to, during the memory program operation, provide a program voltage to a target access line of the plurality of access lines responsive to a determination that an access line of the plurality of access lines has a voltage equal to or greater than a threshold voltage. The threshold voltage is less than the inhibit voltage. | 07-30-2015 |
20150235682 | METHOD AND APPARATUS FOR PRE-CHARGING DATA LINES IN A MEMORY CELL ARRAY - Memories, pre-charge circuits, and methods for pre-charging memory are described. One such method includes providing a voltage to a data line and adjusting the voltage provided to the data line based at least in part on a voltage difference between a target voltage and a voltage of the data line being pre-charged. An example pre-charge circuit includes a voltage generator configured to generate an output voltage having a magnitude based at least in part on a reference voltage and a feedback signal, first and second drivers, and a voltage detector. The voltage detector is configured to determine a voltage difference between the reference voltage and a sample voltage of a data line coupled to the second driver and generate the feedback signal based at least in part on the difference. | 08-20-2015 |
Patent application number | Description | Published |
20120321032 | Bit Scan Circuits and Method in Non-volatile Memory - A circuit for counting in an N-bit string a number of bits M, having a first binary value includes N latch circuits in a daisy chain where each latch circuit has a tag bit that controls each to be either in a no-pass or pass state. Initially the tag bits are set according to the bits of the N-bit string where the first binary value corresponds to a no-pass state. A clock signal having a pulse train is run through the daisy chain to “interrogate” any no-pass latch circuits. It races right through any pass latch circuit. However, for a no-pass latch circuit, a leading pulse while being blocked also resets after a pulse period the tag bit from “no-pass” to “pass” state to allow subsequent pulses to pass. After all no-pass latch circuits have been reset, M is given by the number of missing pulses from the pulse train. | 12-20-2012 |
20130176776 | Charge Cycling By Equalizing and Regulating the Source, Well, and Bit Line Levels During Write Operations for NAND Flash Memory: Program to Verify Transition - In non-volatile memory devices, a write typically consists of an alternating set of pulse and verify operations. At the end of a pulse, the device must be biased properly for an accurate verify, after which the device is re-biased for the next pulse. The intervals between the pulse and verify phases are considered. For the interval after a pulse, but before establishing the verify conditions, the source, bit line, and, optionally, the well levels can be equalized and then regulated at a desired DC level. After a verify phase, but before applying the biasing the memory for the next pulse, the source and bit line levels can be equalized to a DC level. | 07-11-2013 |
20130176777 | Charge Cycling By Equalizing and Regulating the Source, Well, and Bit Line Levels During Write Operations for NAND Flash Memory: Verify to Program Transition - In non-volatile memory devices, a write typically consists of an alternating set of pulse and verify operations. At the end of a pulse, the device must be biased properly for an accurate verify, after which the device is re-biased for the next pulse. The intervals between the pulse and verify phases are considered. For the interval after a pulse, but before establishing the verify conditions, the source, bit line, and, optionally, the well levels can be equalized and then regulated at a desired DC level. After a verify phase, but before applying the biasing the memory for the next pulse, the source and bit line levels can be equalized to a DC level. | 07-11-2013 |
20130258772 | Non-Volatile Memory and Method Having a Memory Array with a High-Speed, Short Bit-Line Portion - A non-volatile memory array is partitioned along the column direction into first and second portions. The first portion has SLC memory cells and the second portion has MLC memory cells. The first portion acts as a fast cache memory for the second portion. The read/write operations of the first portion are further enhanced by coupling to a set of read/write circuits immediately adjacent to the first portion, while the column of each bit line is switchably cut off at the junction between the first and second portions. In this way, the RC constant of the cut off bit line is at a minimum, which translates to faster precharge of the bit line via the read/write circuits. When the second portion is operating, its access to the set of read/write circuits is accomplished by not cutting off each bit line at the junction between the first and second portions. | 10-03-2013 |
20130294162 | Column Redundancy Circuitry for Non-Volatile Memory - In a non-volatile memory circuit, techniques are presented so that bad columns can be ignored and/or replaced during memory data input and output operations. A column redundant circuit for this purpose reduces circuit size and improves performance. User data is grouped in an interleaved manner so that data belonging to consecutive logical address will be distributed into different physical locations. For example, all column data can be physically grouped into, say, 5 divisions and user data can be written into or accessed from one division after another consecutively. Each division has its own clock control. The column redundancy block can generate bad column locations' information and send it to control logic to switch the user clock to a different division clock, thereby skipping bad columns. By controlling the clocks for different columns, the user can directly access good columns without touching bad columns. | 11-07-2013 |
20140003153 | Compact High Speed Sense Amplifier for Non-Volatile Memory | 01-02-2014 |
20140003176 | Compact High Speed Sense Amplifier for Non-Volatile Memory with Reduced layout Area and Power Consumption | 01-02-2014 |
20140022841 | Memory System with Unverified Program Step - In a programming operation that includes repeated bitscan, program, and verify steps, the bitscan steps may be hidden by performing bitscan in parallel with program preparation and program steps. The effect of a program step may be predicted from previous observation so that when a bitscan indicates that the memory cells are close to being programmed, a last programming step may be completed without subsequent verification or bitscan steps. | 01-23-2014 |
20150162825 | Dynamic Load Matching Charge Pump for Reduced Current Consumption - A charge pump is regulated based up its output level. The regulation circuitry adjusts the frequency of the pump's clock based on feedback from pump's output. The pump's clock signal is generated by an oscillator whose frequency depends on a reference voltage level. The reference voltage level is dependent upon a regulation signal. In an example, a transistor whose gate is controlled by the regulation level is part of a series of elements in voltage divider, where the reference value is taken from a node of the divider. | 06-11-2015 |
20150214964 | Multi-Clock Generation Through Phase Locked Loop (PLL) Reference - A circuit for providing a plurality of clock signals of differing frequencies includes: a phase locked loop section including a first voltage controller oscillator, connected to receive a reference clock value and generate therefrom a first voltage level, wherein the first voltage controller oscillator receives the first voltage level and generates therefrom a first clock signal; and one or more second voltage controller oscillators, each connected to receive the first voltage level, a corresponding trim value and a corresponding control voltage and derive therefrom a corresponding second clock signal. | 07-30-2015 |
20150228351 | Self-Adjusting Regulation Current for Memory Array Source Line - To maintain stability of memory array operations, a supplemental current can supply a common source line of a memory array so that the combined current from the memory array and supplemental current is at least a minimum regulation current level. When enabled for sensing operations, a driver circuit maintains the common source line's voltage level. A current subtractor circuit determines the difference between a reference current and a current proportional to the current flowing from the array, where the reference current is proportional to the minimum regulation current. The difference current is then mirrored by a self-adjusting current loop and supplied to the common source line to maintain its current level. | 08-13-2015 |
20150249428 | Methods and Apparatus for Clock Oscillator Temperature Coefficient Trimming - Apparatus and methods are provided for a temperature-compensated oscillator adapted to receive an input reference current. The apparatus and methods include or provide a temperature coefficient control circuit adapted to adjust the input reference current based on temperature information, wherein the temperature coefficient control circuit receives a first signal corresponding to the temperature information at a first signal node, and a second signal corresponding to a trimmed bias signal at a second signal node. | 09-03-2015 |
Patent application number | Description | Published |
20090048756 | MULTI-MODE 2-STROKE/4-STROKE INTERNAL COMBUSTION ENGINE - In a multi-mode, 2-stroke/4-stroke internal combustion engine operation, by switching the engine stroke from 4-stroke operation to 2-stroke operation so that the combustion frequency is doubled, doubling of the engine power is achieved even at the same work output per cycle. In order to meet the demand of extremely high power, the engine operates in 4-stroke boosted SI operation transitioned from 2-stroke HCCI operation at pre-set level of power and crank speed requirements. By combining the multi-stroke (2-stroke HCCI and 4-stroke HCCI) and multi-mode operation (2-stroke HCCI and 4-stroke boosted SI operation), full load range and overall high efficiency with minimal NOx emission are achieved. | 02-19-2009 |
20100275860 | Control architecture and optimal strategy for switching between 2-stroke and 4-stroke modes of HCCI operation - Engine correction inputs to control oscillation in an engine output in a transition between 2-stroke and 4-stroke engine cycle modes of an HCCI engine are determined as follows: for each mode, valve timings which modify the engine output the most upon switching are determined, and a linear engine system model is defined at least partially based on the determined valve timings, which model provides mappings relating initial conditions of the engine and the engine correction inputs to outputs of the engine; initial conditions of the engine corresponding to a switching point for switching between the two modes are determined; desired engine output conditions upon switching between the two modes are specified; and the engine correction inputs are determined by using the determined initial conditions, the desired engine output conditions, and the linear engine system model corresponding to the engine cycle mode in effect upon switching. | 11-04-2010 |
20110081563 | LITHIUM RESERVOIR SYSTEM AND METHOD FOR RECHARGEABLE LITHIUM ION BATTERIES - A lithium-ion battery cell includes at least two working electrodes, each including an active material, an inert material, an electrolyte and a current collector, a first separator region arranged between the at least two working electrodes to separate the at least two working electrodes so that none of the working electrodes are electronically connected within the cell, an auxiliary electrode including a lithium reservoir, and a second separator region arranged between the auxiliary electrode and the at least two working electrodes to separate the auxiliary electrode from the working electrodes so that none of the working electrodes is electronically connected to the auxiliary electrode within the cell. | 04-07-2011 |