Patent application number | Description | Published |
20130318084 | PROCESSING STRUCTURED AND UNSTRUCTURED DATA USING OFFLOAD PROCESSORS - Methods of processing structured data, unstructured data, or both are disclosed. Processing structured data can include providing an in-memory database with at least one of a plurality of modules connected to a memory bus of a server; executing database functions with at least one processor on the module; and directing database queries to the at least one module with a CPU of the server. Processing unstructured data can include executing data processing tasks with a CPU connected to a memory bus; and directing parallel computation tasks to a plurality of modules connected to the memory bus. | 11-28-2013 |
20130318119 | PROCESSING STRUCTURED AND UNSTRUCTURED DATA USING OFFLOAD PROCESSORS - A data processing system for unstructured data is disclosed. A plurality of modules can be connected to a memory bus, each including at least one processor. A central processing unit (CPU) can be connected to the modules by the memory bus, with the CPU configured to process computationally intensive data processing tasks while directing parallel computation tasks to a plurality of the modules. | 11-28-2013 |
20130318268 | OFFLOADING OF COMPUTATION FOR RACK LEVEL SERVERS AND CORRESPONDING METHODS AND SYSTEMS - A distributed server system for handling multiple networked applications is disclosed. Systems can include at least one main processor; a plurality of offload processors connected to a memory bus; an arbiter connected to each of the plurality of offload processors, the arbiter configured to schedule resource priority for instructions or data received from the memory bus; and a virtual switch respectively connected to the main processor and the plurality of offload processors using the memory bus, with the virtual switch capable of receiving memory read/write data over the memory bus, and further directing at least some memory read/write data to the arbiter. | 11-28-2013 |
20130318269 | PROCESSING STRUCTURED AND UNSTRUCTURED DATA USING OFFLOAD PROCESSORS - Methods of processing structured data are disclosed that can include providing a plurality of XIMM modules connected to a memory bus in a first server, with the XIMM modules each respectively having a DMA slave module connected to the memory bus and an arbiter for scheduling tasks, with the XIMM modules further providing an in-memory database; and connecting a central processing unit (CPU) in the first server to the XIMM modules by the memory bus, with the CPU arranged to process and direct structured queries to the plurality of XIMM modules. | 11-28-2013 |
20130318275 | OFFLOADING OF COMPUTATION FOR RACK LEVEL SERVERS AND CORRESPONDING METHODS AND SYSTEMS - A method is disclosed that includes writing data to predetermined physical addresses of a system memory, the data including metadata that identifies a processing type; configuring a processor module to include the predetermined physical addresses, the processor module being physically connected to the memory bus by a memory module connection; and processing the write data according to the processing type with an offload processor mounted on the processor module. | 11-28-2013 |
20130318276 | OFFLOADING OF COMPUTATION FOR RACK LEVEL SERVERS AND CORRESPONDING METHODS AND SYSTEMS - A system is disclosed that can include at least one processor module connectable to a memory bus. The processor module can include at least one memory, at least one offload processor mounted on the processor module, and configured to execute operations on data received over the memory bus, and to output context data to the memory and read context data from the memory, and a hardware scheduling logic mounted on the module and configured to control operations of the at least one processor. | 11-28-2013 |
20130318277 | PROCESSING STRUCTURED AND UNSTRUCTURED DATA USING OFFLOAD PROCESSORS - A structured data processing system is disclosed that can include a plurality of XIMM modules connected to a memory bus in a first server, with the XIMM modules each respectively having a DMA slave module connected to the memory bus and an arbiter for scheduling tasks, with the XIMM modules providing an in-memory database; and a central processing unit (CPU) in the first server connected to the XIMM modules by the memory bus, with the CPU arranged to process and direct structured queries to the plurality of XIMM modules. | 11-28-2013 |
20130318280 | OFFLOADING OF COMPUTATION FOR RACK LEVEL SERVERS AND CORRESPONDING METHODS AND SYSTEMS - Methods for handling multiple networked applications using a distributed server system are disclosed. Methods can include providing at least one main processor and a plurality of offload processors connected to a memory bus; providing an arbiter connected to each of the plurality of offload processors, the arbiter capable of scheduling resource priority for instructions or data received from the memory bus; and operating a virtual switch respectively connected to the main processor and the plurality of offload processors using the memory bus, with the virtual switch capable of receiving memory read/write data over the memory bus; and directing at least some memory read/write data to the arbiter from the virtual switch. | 11-28-2013 |
20130346469 | OFFLOADING OF COMPUTATION FOR RACK LEVEL SERVERS AND CORRESPONDING METHODS AND SYSTEMS - A method for handling multiple networked applications using a distributed server system is disclosed. The method can include providing at least one main processor and a plurality of offload processors connected to a memory bus; and operating a virtual switch respectively connected to the main processor and the plurality of offload processors using the memory bus, with the virtual switch receiving memory read/write data over the memory bus. | 12-26-2013 |
20130347110 | EFFICIENT PACKET HANDLING, REDIRECTION, AND INSPECTION USING OFFLOAD PROCESSORS - A packet handling system is disclosed that can include at least one main processor; a plurality of offload processors connected to a memory bus and configured to provide security related services on packets prior to redirection to the main processor; and a virtual switch respectively connected to the main processor and the plurality of offload processors using the memory bus, the virtual switch configured to receive memory read/write data over the memory bus. | 12-26-2013 |
20140157396 | EFFICIENT PACKET HANDLING, REDIRECTION, AND INSPECTION USING OFFLOAD PROCESSORS - A method for handling packets is disclosed. The method can include providing at least one main processor connected to a plurality of offload processors by a memory bus; configuring the offload processors to provide security related services on packets prior to redirection to the main processor; and operating a virtual switch respectively connected to the main processor and the plurality of offload processors using the memory bus, with the virtual switch capable of receiving memory read/write data over the memory bus. | 06-05-2014 |
20140157397 | EFFICIENT PACKET HANDLING, REDIRECTION, AND INSPECTION USING OFFLOAD PROCESSORS - A packet handling system is disclosed that can include at least one main processor, a plurality of offload processors connected to a memory bus and configured to provide security related services on packets prior to redirection to the main processor; an arbiter connected to each of the plurality of offload processors, the arbiter capable of scheduling resource priority for instructions or data received from the memory bus; and a virtual switch respectively connected to the main processor and the plurality of offload processors using the memory bus, with the virtual switch capable of receiving memory read/write data over the memory bus, and further directing at least some memory read/write data to the arbiter. | 06-05-2014 |
20140165196 | EFFICIENT PACKET HANDLING, REDIRECTION, AND INSPECTION USING OFFLOAD PROCESSORS - Method for handling packets are disclosed that can include providing at least one main processor connected to a plurality of offload processors by a memory bus; providing an arbiter connected to each of the plurality of offload processors, the arbiter capable of scheduling resource priority for instructions or data received from the memory bus; configuring the offload processors to provide security related services on packets prior to redirection to the main processor; operating a virtual switch respectively connected to the main processor and the plurality of offload processors using the memory bus, with the virtual switch capable of receiving memory read/write data over the memory bus; and directing at least some memory read/write data to the arbiter from the virtual switch. | 06-12-2014 |
20140198652 | Scheduling and Traffic Management with Offload Processors - A scheduling system for a packet processing system is disclosed. The system can include a classification circuit connected to a memory bus and configurable to classify network packets, placing the classified network packets into first multiple input/output queues, a scheduling circuit for reordering the network packets received from the classification circuit through the first multiple input/output queues and placing the reordered network packets into second multiple input/output queues, an arbitration circuit for directing network packets received from the scheduling circuit through the second multiple input/output queues to multiple output ports, and multiple offload processors, each coupled to at least one of the multiple output ports, the offload processors configured to modify the network packets. | 07-17-2014 |
20140198653 | Scheduling and Traffic Management with Offload Processors - A method for scheduling packet processing is disclosed. The method can include classifying network packets based on session metadata and placing the classified network packets into first multiple input/output queues, with network packets transported to a classification circuit using a memory bus having a defined memory transport protocol, reordering network packets received from the first multiple input/output queues using a scheduling circuit and placing the reordered network packets into a second multiple input/output queues, directing network packets received from the scheduling circuit through the second multiple input/output queues to multiple output ports using an arbitration circuit, and modifying network packets using multiple offload processors, each offload processor coupled to at least one of the multiple output ports, the offload processors configured to direct modified network packets back to the memory bus. | 07-17-2014 |
20140198799 | Scheduling and Traffic Management with Offload Processors - A method for providing scheduling services for network packet processing using a memory bus connected module is disclosed. The method can include transferring network packets to the module through a memory bus connection, reordering network packets received from the memory bus connection with a scheduling circuit and placing the reordered network packets into multiple input/output queues, and modifying reordered network packets placed into multiple input/output queues using multiple offload processors connected to the memory bus. | 07-17-2014 |
20140198803 | Scheduling and Traffic Management with Offload Processors - A memory bus connected module for scheduling services for network packet processing is disclosed. The module can include a memory bus connection, a scheduling circuit configured to reorder network packets received from the memory bus connection and place the reordered network packets into multiple input/output queues, and multiple offload processors connected to the memory bus connection, each offload processor configured to modify network packets in the multiple input/output queues. | 07-17-2014 |
20140201303 | Network Overlay System and Method Using Offload Processors - An input-output (IO) virtualization system connectable to a network is disclosed. The system can include a second virtual switch connected to a memory bus and configured to receive network packets from a first virtual switch, and an offload processor module supporting the second virtual switch, the offload processor module further comprising at least one offload processor configured to modify network packets and direct the modified network packets to the first virtual switch through the memory bus. | 07-17-2014 |
20140201304 | Network Overlay System and Method Using Offload Processors - A method for processing data is disclosed. The method can include transporting data to a second virtual switch from a first virtual switch using a memory bus having a defined memory transport protocol, writing the transported data to a target memory location, and processing the data written to the target memory location with at least one offload processor included on an offload processor module. | 07-17-2014 |
20140201305 | Network Overlay System and Method Using Offload Processors - A memory bus connected module, connectable to a first virtual switch for providing input-output (IO) virtualization services is disclosed. The module can include a second virtual switch coupled to the first virtual switch via a memory bus connection, a plurality of offload processors coupled to the memory bus connection, and at least one memory unit connected to, and separately addressable by, the multiple offload processors, and configured to receive data directed to a specific memory address space for processing by at least one of the offload processors. | 07-17-2014 |
20140201309 | Network Overlay System and Method Using Offload Processors - A method for providing network overlay services capable of processing network packets having associated packet metadata is disclosed. The method can include writing packets to a specific memory location accessible by at least one offload processor, with packets transported using a memory bus having a defined memory transport protocol, modifying packet metadata of the packets written to the specific memory location with the at least one offload processor, without requiring modification of the packets by a host processor, and sending the modified packets to the memory bus. | 07-17-2014 |
20140201310 | Network Overlay System and Method Using Offload Processors - A memory bus connected module for providing network overlay services is disclosed. The module comprising can include a memory bus connection, multiple offload processors coupled to the memory bus connection, each offload processor configured to convert incoming packets having a first network protocol to outgoing packets having a second network protocol, and control logic connected to the multiple offload processors for determining order of packet conversion by respective task execution of the multiple offload processors. | 07-17-2014 |
20140201390 | Network Overlay System and Method Using Offload Processors - A network overlay system capable of processing network packets having metadata is disclosed. The system can include a data transport module configurable to direct network packets based on network identifier tags, an offload processor module connected to a memory bus and including at least one offload processor capable of modifying segregated network packets, and a memory bus connected between the data transport module and the at least one offload processor to support transport of network packets to the offload processor for modification. | 07-17-2014 |
20140201402 | Context Switching with Offload Processors - A memory bus connected module with context switching capability is described. The module can include a memory bus connection compatible with a memory bus socket, a plurality of offload processors attached to the module and connected to a memory bus, with each offload processor having a cache with an associated cache state, a context memory attached to the module and connected to the offload processors, and a scheduling circuit configured to direct a transfer of a cache state between at least one of the offload processors and the context memory. | 07-17-2014 |
20140201404 | OFFLOAD PROCESSOR MODULES FOR CONNECTION TO SYSTEM MEMORY, AND CORRESPONDING METHODS AND SYSTEMS - A system can include at least one offload processor having a data cache, the offload processor including a slave interface configured to receive write data and provide read data over a memory bus; an offload processor module including context memory and a bus controller connected to the slave interface; and logic coupled to the offload processor and context memory and configured to detect predetermined write operations over the memory bus; wherein the offload processor is configured to execute operations on data received over the memory bus, and to output context data to the context memory, and read context data from the context memory. | 07-17-2014 |
20140201408 | OFFLOAD PROCESSOR MODULES FOR CONNECTION TO SYSTEM MEMORY, AND CORRESPONDING METHODS AND SYSTEMS - A system can include at least one processor module, including an in-line module connector configured to physically connect the processor module to at least one in-line memory slot of a system memory bus; at least one memory; at least one offload processor mounted on the module, and configured to execute operations on data received over the system memory bus, and to output context data to the memory, and read context data from the memory; and hardware scheduling logic including an arbiter that arbitrates between conflicting data access requirements within the processor module, and a scheduler to order computing tasks, both arbiter and scheduler being mounted on the module and configured to control operations of the at least one processor. | 07-17-2014 |
20140201409 | OFFLOAD PROCESSOR MODULES FOR CONNECTION TO SYSTEM MEMORY, AND CORRESPONDING METHODS AND SYSTEMS - A processor module can include an in-line module connector configured to physically connect to an in-line memory slot of a system memory bus; a data interface configured to receive write data from the system memory bus, via the in-line module connector, and according to a predetermined protocol; and at least one offload processor configured to process the write data according to instruction data within the write data; and wherein hardware scheduling logic mounted in the processor module include an arbiter that arbitrates between conflicting data access requirements within the processor module, and a scheduler to order computing tasks, both arbiter and scheduler being mounted on the in-line module and configured to control operations of the at least one offload processor. | 07-17-2014 |
20140201416 | OFFLOAD PROCESSOR MODULES FOR CONNECTION TO SYSTEM MEMORY, AND CORRESPONDING METHODS AND SYSTEMS - A method can include receiving write data over a system memory bus via an in-line module connector, the write data including a metadata portion identifying a processing to be performed on at least a portion of the write data; performing the processing on at least a portion of the write data with at least one offload processor mounted on a module having the in-line module connector to generate processed data; and transmitting the processed data over the system memory bus; wherein the system memory bus is further connected to at least one processor connector configured to receive at least one host processor different from the at least one offload processor. | 07-17-2014 |
20140201417 | OFFLOAD PROCESSOR MODULES FOR CONNECTION TO SYSTEM MEMORY, AND CORRESPONDING METHODS AND SYSTEMS - A system can include a host processor connected to memory via a system memory bus; and at least one offload processor module, including at least one offload processor mounted on the offload processor module, and configured to execute operations on data received over the system memory bus, and to output context data to memory, and read context data from the memory, and hardware scheduling logic mounted on the module and configured to control operations of the at least one offload processor. | 07-17-2014 |
20140201453 | Context Switching with Offload Processors - A context switching cache system is disclosed. The system can include a plurality of offload processors connected to a memory bus, each offload processor having a cache with an associated cache state, a context memory coupled to the offload processors, and a scheduling circuit configured to direct transfer of a cache state between at least one of the offload processors and the context memory. | 07-17-2014 |
20140201461 | Context Switching with Offload Processors - A method for context switching of multiple offload processors coupled to receive data for processing over a memory bus is disclosed. The method can include directing storage of a cache state, via a bulk read from a cache of at least one of a plurality of offload processors into a context memory, by operation of a scheduling circuit, with any virtual and physical memory locations of the cache state being aligned, and subsequently directing transfer of the cache state to at least one of the offload processors for processing, by operation of the scheduling circuit. | 07-17-2014 |
20140201761 | Context Switching with Offload Processors - A method for context switching of multiple offload processors is disclosed. The method can include receiving network packets for processing through a memory bus connected socket, organizing the network packets into multiple sessions for processing, suspending processing of at least one session by reading a cache state of at least one of the offload processor into a context memory by operation of a scheduling circuit, with virtual memory locations and physical cache locations being aligned, and subsequently directing transfer of the cache state to at least one of the offload processors for processing by operation of the scheduling circuit. | 07-17-2014 |
20140351481 | OFFLOADING OF COMPUTATION FOR RACK LEVEL SERVERS AND CORRESPONDING METHODS AND SYSTEMS - A distributed server system is disclosed that can handle multiple networked applications. A system can include at least one main processor; a plurality of offload processors connected to a memory bus; and a virtual switch respectively connected to the main processor and the plurality of offload processors using the memory bus, with the virtual switch configured to receive memory read/write data over the memory bus. | 11-27-2014 |