Patent application number | Description | Published |
20100058094 | DATA PROCESSING APPARATUS - A data processing apparatus includes a CPU including a register, a cache memory, a main memory configured to exchange data with the cache memory, a control part configured to control the exchanging of data between the main memory and the cache memory, and a power supply part configured to supply power to the register, the cache memory, and the main memory. The register, the cache memory, and the main memory are each configured to store data and maintain the stored data therein without being supplied with the power from the power supply part. The control part is configured to stop the CPU from accessing the register, the cache memory, and the main memory where an abnormality occurs in the power supply part. | 03-04-2010 |
20100067313 | MEMORY DEVICE - A memory device that can include a power-supply voltage detector that detects power-supply voltage values and that outputs a detection result indicating which power-supply voltage value is detected; a data-rate setter that sets data rates corresponding to the detection result of the power-supply voltage detector, in synchronization with a rising edge or falling edge of a clock signal; and a memory cell array that performs reading/writing at the data rates set by the data-rate setter. | 03-18-2010 |
20100088545 | COMPUTER APPARATUS AND PROCESSOR DIAGNOSTIC METHOD - A computer apparatus includes a first processor, a second processor, and a main memory. The computer apparatus further includes a memory-diagnostic unit, a diagnostic-program loading unit, and a defective-function identifying unit. The memory-diagnostic unit causes the second processor to execute a memory-diagnostic program to diagnose the main memory, and identifies a defective area in the main memory. The diagnostic-program loading unit loads a processor-diagnostic program for diagnosing a plurality of functions of the first processor into an area of the main memory other than the defective area identified by the memory-diagnostic unit. The defective-function identifying unit causes the second processor to execute the processor-diagnostic program loaded by the diagnostic-program loading unit, and identifies a defective function that is disabled from the functions of the first processor. | 04-08-2010 |
20100088558 | COMPUTER APPARATUS - A computer apparatus includes a main memory, a first memory diagnosis unit that determines a faulty area in the main memory by executing a first memory diagnostic program, and a storage unit that stores a relocatable second memory diagnostic program. Moreover, the computer apparatus includes a second memory diagnosis unit, that loads the second memory diagnostic program into areas of the main memory other than the faulty area determined by the first memory diagnosis unit. | 04-08-2010 |
20100088559 | COMPUTER SYSTEM AND MEMORY USE SETTING PROGRAM - A computer system including: a memory configured to store various kinds of data; a use setting data memory means for storing use setting data indicating a use of each of a plurality of memory blocks into which the memory is divided by a certain length; a memory diagnosis means for diagnosing the memory so as to detect a bad area in each of the memory blocks; and a memory use setting means for setting the use setting data of each of the memory blocks stored in the use setting data memory means in accordance with a result of detecting the bad area in each of the memory blocks by means of the memory diagnosis means. | 04-08-2010 |
20100180152 | INFORMATION PROCESSING DEVICE, STORAGE CONTROL DEVICE, AND STORAGE CONTROL METHOD - An information processing device includes a first storage section | 07-15-2010 |
20100205394 | SEMICONDUCTOR STORAGE DEVICE AND CONTROL METHOD THEREOF - When an address indicating an access destination of a data storing unit, and a command indicating a content of a process for the address are input, block information corresponding to the input address is output from an information holding unit. Whether or not to execute the command for the address is decided on the basis of the output block information and the input command. | 08-12-2010 |
20110010508 | Memory system and information processing device - A memory system includes a first memory that is used as a main memory of a target device, a second memory that has an access speed lower than that of the first memory, a securing section that secures a predetermined area of the first memory as a temporary storage area of the second memory, and a memory control section that receives an instruction to write data into the second memory, temporarily stores the data into the first memory and also transfers the stored data from the first memory to the second memory. | 01-13-2011 |
20110314347 | MEMORY ERROR DETECTING APPARATUS AND METHOD - A memory error detecting apparatus for detecting an error of a subject memory, the memory error detecting apparatus includes a memory bus connected to the subject memory, a mirror memory connected to the memory bus so as to receive the same data as data to be written into and read from the subject memory, the received data being written into the mirror memory, an address acquiring portion configured to acquire an address related to the data written into the subject memory, a mirror memory controller configured to control data writing or reading to or from the mirror memory on the basis of the acquired address, a comparator configured to compare data read from the subject memory and data read from the mirror memory, and an error detector configured to detect a data error on the basis of a result of the comparison. | 12-22-2011 |
20120254663 | SEMICONDUCTOR MEMORY DEVICE AND INFORMATION PROCESSING APPARATUS INCLUDING THE SAME - A semiconductor memory device is disclosed that includes an ODT circuit configured to be connected to a bus which transmits a data signal or a data strobe signal between a memory block and an input-output terminal; a first switch configured to be inserted into the bus between the memory block and the ODT circuit; a mode controller configured to switch off the first switch during a test of the memory block; and an oscillator configured to be connected to the ODT circuit, wherein a test signal is supplied to the ODT circuit from the oscillator during the test of the memory block. | 10-04-2012 |
20130077426 | SEMICONDUCTOR STORAGE APPARATUS AND SEMICONDUCTOR INTEGRATED CIRCUIT - In a semiconductor storage apparatus, an internal address generation unit generates, when receiving successive first and second external addresses, from the second external address an internal address for selecting any of the memory cells connected to bit lines and word lines except the bit line and word line connected to a memory cell to be selected according to the first external address. When receiving the successive external addresses, a memory cell connected to the same bit line and word line is not continuously selected, and erroneous readout due to rewriting of a value of the memory cell in a non-selected state is suppressed. | 03-28-2013 |
20130145233 | MEMORY MODULE AND SEMICONDUCTOR STORAGE DEVICE - A memory module includes a plurality of memory chips stacked on top of one another, each of the plurality of memory chips including a memory cell unit that is divided into a plurality of blocks, and an address scrambling circuit that processes an input address signal and that selects a block to be operated. | 06-06-2013 |