Ong, MY
Chee Peng Ong, Ayer Keroh MY
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20140285229 | Testing Integrated Circuit Packaging for Shorts - An electronic package that has an array of pins may be tested for shorts and continuity in a parallel manner. The array of pins are allocated to four or more groups of pins such that each pin in each group is not adjacent to a pin from its own group of pins. One of the groups of pins is tested for continuity while placing a reference voltage level on all of the pins in the other groups of pins. A separate current source is coupled to each pin and a resultant voltage is measured. A short between one of the pins in the first group and a pin in one of the other groups can be detected when the resultant voltage on one of the pins in the first group is approximately equal to the reference voltage. Group-wise testing is repeated until all groups have been tested. | 09-25-2014 |
20140292361 | Testing Integrated Circuit Packaging for Output Short Circuit Current - An electronic package having multiple pins may be tested in parallel for output short circuit current by simulating a direct short to ground by simultaneously connecting multiple output pins directly to ground in order to active a current limiter associated with each of the output pins. The pins are then connected to a resistive connection to ground via a set of resistors; the direct ground is then removed, such that the current limiter associated with each of the output pins remains activated. A voltage drop across each of the set of resistors is measured simultaneously. An output short circuit current fault is indicated when the voltage drop across any of the resistors exceeds a threshold value corresponding to a maximum output short circuit current value | 10-02-2014 |
Eng Long Ong, Klang MY
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20150218352 | GLOVE HAVING EXCELLENT CHEMICAL RESISTANCE AND COMPOSITION FOR SAID GLOVE - An emulsion composition for producing a glove, the composition containing: (1) a carboxylated acrylonitrile-butadiene elastomer, comprising 30 to 40% by weight of acrylonitrile residues and 3 to 8% by weight of unsaturated carboxylic acid residues, having an elemental sulfur content detected by neutralization titration of a combusted product of the elastomer of not more than 1% by weight of the elastomer weight, and having a Mooney viscosity (ML | 08-06-2015 |
Jenny Shio Yin Ong, Bayan Lepas MY
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20150091180 | PACKAGE ON WIDE I/O SILICON - An apparatus including a die including a device side and an opposite backside, first contacts on the backside and a through vias from the device side to the first contacts and second contacts on the backside of the die or on at least two opposing sidewalls of the die; a secondary die coupled to the first plurality of contacts; and a carrier including carrier contact points operable for mounting the carrier to a substrate. A method including forming a first portion of a carrier adjacent a device side of a die and including carrier contact points operable for mounting the carrier to a substrate; and forming a second portion including second carrier contact points connected to contacts on the backside of the die or on at least two opposing sidewalls of the die; and coupling a secondary die to the second carrier contact points. | 04-02-2015 |
Lan Yit Ong, Selangor MY
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20150228601 | SUBSTRATE WITH CORNER CUT-OUTS AND SEMICONDUCTOR DEVICE ASSEMBLED THEREWITH - A semiconductor device is assembled from a rectangular substrate sheet. The substrate sheet has die mounting pads accessible from a first side and package mounting pads accessible from an opposite side. Corner regions of the substrate sheet have receding edges. A semiconductor die is attached to the substrate sheet such that electrodes or bonding pads of the die are mounted to respective die mounting pads of the substrate sheet. An encapsulating material covers the semiconductor die and the first side of the substrate sheet. Corner covering sections of the encapsulating material further cover the receding edges of the corner regions. | 08-13-2015 |
Mee-Choo Ong, Batu Maung MY
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20140185393 | DESIGN FOR TEST (DFT) READ SPEED THROUGH TRANSITION DETECTOR IN BUILT-IN SELF-TEST (BIST) SORT - A memory is disclosed that can operate in a normal mode of operation or a testing mode of operation. In the testing mode of operation, the memory can measure various benchmarks of performance, such as read speed. The memory can perform an asynchronous read operation to read a word of electronic data that corresponds to an address or a page read operation in which multiple asynchronous read operations are performed to read multiple words of electronic data, also referred to as a page of electronic data, that correspond to multiple addresses. The memory can measure a time required, referred to as read speed, to read the word of electronic data or the multiple words of electronic data from the memory. In the normal mode of operation, the memory can perform the asynchronous read operation, the page read operation, an asynchronous write operation in which a word of electronic data is stored into the memory that correspond to the address, or a page write operation in which a page electronic data is stored into the memory that correspond to the multiple addresses. | 07-03-2014 |
Meng Tong Ong, Melaka MY
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20140110835 | Bump Package and Methods of Formation Thereof - In accordance with an embodiment of the present invention, a semiconductor package includes a semiconductor chip and a bump. The semiconductor chip has a contact pad on a major surface. The bump is disposed on the contact pad of the semiconductor chip. A solder layer is disposed on sidewalls of the bump. | 04-24-2014 |
20140299981 | High Power Single-Die Semiconductor Package - A semiconductor package includes a single semiconductor die and an electrically and thermally conductive base. The single semiconductor die includes a semiconductor body having opposing first and second surfaces and insulated sides between the first and second surfaces. The single semiconductor die further includes a first electrode at the first surface and a second electrode at the second surface. The single semiconductor die has a defined thickness measured between the first and second surfaces, a defined width measured along one of the insulated sides, and a defined length measured along another one of the insulated sides. The base is attached to the second electrode at the second surface of the single semiconductor die and has the same length and width as the single semiconductor die. | 10-09-2014 |
20140312497 | Molding Material and Method for Packaging Semiconductor Chips - A method and apparatus for packaging a semiconductor chip is presented. A semiconductor device includes a chip, a lead, and an encapsulant. The encapsulant includes a stabilization layer, a laminate molding layer connected to the stabilization layer, and a conductive strip connected to the laminate molding layer. The conductive strip electrically connects the contact area of the chip to the lead. | 10-23-2014 |
Shue Ling Ong, Kuala Sepetang MY
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20140159157 | ANTENNA DIODE CIRCUITRY AND METHOD OF MANUFACTURE - An integrated circuit with an antenna diode is described. The integrated circuit includes a substrate, a transistor, first and second diffusion regions, and a dummy gate. The transistor and the first and second diffusion regions may be formed within the substrate. The transistor has its gate structure disposed on the substrate. The dummy gate structure may be disposed on a region of the substrate such that it separates the first diffusion region from the second diffusion region. The dummy gate structure may also be coupled to the transistor gate structure. | 06-12-2014 |
Tiam Sen Ong, Semabok Melaka MY
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20160126163 | LEAD FRAME STRIP WITH MOLDING COMPOUND CHANNELS - A lead frame strip has a plurality of unit lead frames. Each of the unit lead frames has a periphery structure connecting adjacent ones of the unit lead frames, a die paddle inside of the periphery structure, a plurality of leads connected to the periphery structure and extending towards the die paddle, and a molding compound channel in the periphery structure configured to guide liquefied molding material. The lead frame strip is processed by attaching a semiconductor die to each of the die paddles, electrically connecting each of the semiconductor dies to the leads, and forming a liquefied molding compound on each of the unit lead frames. The liquefied molding compound is formed such that the liquefied molding compound encapsulates the semiconductor dies and flows into the molding compound channels thereby forming molding extensions that extend onto the periphery structures. | 05-05-2016 |
Wei-Kent Ong, Bayan Lepas MY
Patent application number | Description | Published |
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20140185393 | DESIGN FOR TEST (DFT) READ SPEED THROUGH TRANSITION DETECTOR IN BUILT-IN SELF-TEST (BIST) SORT - A memory is disclosed that can operate in a normal mode of operation or a testing mode of operation. In the testing mode of operation, the memory can measure various benchmarks of performance, such as read speed. The memory can perform an asynchronous read operation to read a word of electronic data that corresponds to an address or a page read operation in which multiple asynchronous read operations are performed to read multiple words of electronic data, also referred to as a page of electronic data, that correspond to multiple addresses. The memory can measure a time required, referred to as read speed, to read the word of electronic data or the multiple words of electronic data from the memory. In the normal mode of operation, the memory can perform the asynchronous read operation, the page read operation, an asynchronous write operation in which a word of electronic data is stored into the memory that correspond to the address, or a page write operation in which a page electronic data is stored into the memory that correspond to the multiple addresses. | 07-03-2014 |