Patent application number | Description | Published |
20120276657 | METHOD OF PATTERNING OF MAGNETIC TUNNEL JUNCTIONS - Embodiments of the invention generally relate to methods for fabricating devices on semiconductor substrates. More specifically, embodiments of the invention relate to methods of patterning magnetic materials. Certain embodiments described herein use a reducing chemistry containing a hydrogen gas or hydrogen containing gas with an optional dilution gas at temperatures ranging from 20 to 300 degrees Celsius at a substrate bias less than 1,000 DC voltage to reduce the amount of sputtering and redeposition. Exemplary hydrogen containing gases which may be used with the embodiments described herein include NH | 11-01-2012 |
20140183159 | METHOD OF OBTAINING PATTERS IN AN ANTIREFLECTIVE LAYER - The invention relates to the field of production in thin coatings of electronic devices and/or MEMS and relates to an improved method for forming a pattern in a thin SiARC anti-reflective coating, comprising the doping by deposition of such SiARC coating covered with a resist pattern through a protective coating of the resist pattern, then etching the doped zones of the SiARC coating (FIG. | 07-03-2014 |
20140187035 | METHOD OF ETCHING A POROUS DIELECTRIC MATERIAL - The invention relates to a method of etching a layer of porous dielectric material, characterized in that the etching is performed in a plasma formed from at least one silicon-based gas mixed with oxygen (O | 07-03-2014 |
20140187046 | METHOD FOR FORMING SPACERS FOR A TRANSITOR GATE - The invention relates to a method for forming spacers for a gate of a field effect transistor, the gate being situated above a layer of semiconductor material, comprising a step of forming a layer of nitride covering the transistor gate, the method being characterized in that it comprises:
| 07-03-2014 |
20140273292 | METHODS OF FORMING SILICON NITRIDE SPACERS - Embodiments of methods of forming silicon nitride spacers are provided herein. In some embodiments, a method of forming silicon nitride spacers atop a substrate includes: depositing a silicon nitride layer atop an exposed silicon containing layer and an at least partially formed gate stack disposed atop a substrate; modifying a portion of the silicon nitride layer by exposing the silicon nitride layer to a hydrogen or helium containing plasma that is substantially free of fluorine; and removing the modified portion of the silicon nitride layer by performing a wet cleaning process to form the silicon nitride spacers, wherein the wet cleaning process removes the modified portion of the silicon nitride layer selectively to the silicon containing layer. | 09-18-2014 |
20140273297 | EMBEDDED TEST STRUCTURE FOR TRIMMING PROCESS CONTROL - In some embodiments, a method of controlling a photoresist trimming process in a semiconductor manufacturing process may include forming a photoresist layer atop a first surface of a substrate, wherein the photoresist layer comprises a lower layer having a first pattern to be etched into the first surface of the substrate, and an upper layer having a second pattern that is not etched into the first surface of the substrate; trimming the photoresist layer in a direction parallel to the first surface of the substrate; measuring a trim rate of the second pattern using an optical measuring tool during the trimming process; and correlating the trim rate of the second pattern to a trim rate of the first pattern to control the trim rate of the first pattern during the trimming process. | 09-18-2014 |
20140335695 | EXTERNAL UV LIGHT SOURCES TO MINIMIZE ASYMMETRIC RESIST PATTERN TRIMMING RATE FOR THREE DIMENSIONAL SEMICONDUCTOR CHIP MANUFACTURE - Embodiments of the present invention provide an apparatus and methods for forming stair-like structures in manufacturing three dimensional (3D) stacking of semiconductor chips. In one embodiment, a method of forming stair-like structures on a substrate includes performing a trimming process on a substrate to trim a patterned photoresist layer disposed on a film stack from a first width to a second width in a processing chamber, wherein the patterned photoresist layer exposes a portion of the film stack uncovered by the patterned photoresist layer during the trimming process, wherein the trimming process further comprises supplying a trimming gas mixture including at least an oxygen containing gas, and providing a light energy in the trimming gas mixture to an edge of the substrate during the trimming process. | 11-13-2014 |
20150228495 | PLASMA ETCHING PROCESS - A method and system are provided for etching a layer to be etched in a plasma etching reactor, including: forming a reactive layer by injection of at least one reactive gas to form a reactive gas plasma, which forms, together with the layer to be etched, a reactive layer which goes into the layer to be etched during etching of said layer to be etched, wherein the reactive layer reaches a steady state thickness upon completion of a determined duration of said injection; said injection being interrupted before said determined duration has elapsed so that, upon completion of the forming of the reactive layer, the thickness of the reactive layer is smaller than said steady state thickness; and removing the reactive layer by injection of at least one inert gas to form an inert gas plasma, which makes it possible to remove only the reactive layer. | 08-13-2015 |