Patent application number | Description | Published |
20090157377 | METHOD AND SYSTEM FOR MULTIPROCESSOR EMULATION ON A MULTIPROCESSOR HOST SYSTEM - A method (and system) for executing a multiprocessor program written for a target instruction set architecture on a host computing system having a plurality of processors designed to process instructions of a second instruction set architecture, includes representing each portion of the program designed to run on a processor of the target computing system as one or more program threads to be executed on the host computing system. | 06-18-2009 |
20110191095 | METHOD AND SYSTEM FOR EFFICIENT EMULATION OF MULTIPROCESSOR ADDRESS TRANSLATION ON A MULTIPROCESSOR - A method (and structure) of mapping a memory addressing of a multiprocessing system when it is emulated using a virtual memory addressing of another multiprocessing system includes accessing a local lookaside table (LLT) on a target processor with a target virtual memory address. Whether there is a “miss” in the LLT is determined and, with the miss determined in the LLT, a lock for a global page table is obtained. | 08-04-2011 |
20110209154 | THREAD SPECULATIVE EXECUTION AND ASYNCHRONOUS CONFLICT EVENTS - In an embodiment, asynchronous conflict events are received during a previous rollback period. Each of the asynchronous conflict events represent conflicts encountered by speculative execution of a first plurality of work units and may be received out-of-order. During a current rollback period, a first work unit is determined whose speculative execution raised one of the asynchronous conflict events, and the first work unit is older than all other of the first plurality of work units. A second plurality of work units are determined, whose ages are equal to or older than the first work unit, wherein each of the second plurality of work units are assigned to respective executing threads. Rollbacks of the second plurality of work units are performed. After the rollbacks of the second plurality of work units are performed, speculative executions of the second plurality of work units are initiated in age order, from oldest to youngest. | 08-25-2011 |
20120089820 | HYBRID MECHANISM FOR MORE EFFICIENT EMULATION AND METHOD THEREFOR - In a host system, a method for using instruction scheduling to efficiently emulate the operation of a target computing syste includes preparing, on the host system, an instruction sequence to interpret an instruction written for execution on the target computing system. An instruction scheduling on the instruction sequence is performed, to achieve an efficient instruction level parallelism, for the host system. A separate and independent instruction sequence is inserted, which, when executed simultaneously with the instruction sequence, performs to copy to a separate location a minimum instruction sequence necessary to execute an intent of an interpreted target instruction, the interpreted target instruction being a translation; and modifies the interpreter code such that a next interpretation of the target instruction results in execution of the translated version, thereby removing execution of interpreter overhead. | 04-12-2012 |
Patent application number | Description | Published |
20090083702 | System and Method for Selective Code Generation Optimization for an Advanced Dual-Representation Polyhedral Loop Transformation Framework - A system and method for selective code generation optimization for an advanced dual-representation polyhedral loop transformation framework are provided. The mechanisms of the illustrative embodiments address the weaknesses of the known polyhedral loop transformation based approaches by providing mechanisms for performing code generation transformations on individual statement instances in an intermediate representation generated by the polyhedral loop transformation optimization of the source code. These code generation transformations have the important property that they do not change program order of the statements in the intermediate representation. This property allows the result of the code generation transformations to be provided back to the polyhedral loop transformation mechanisms in a program statement view, via a new re-entrance path of the illustrative embodiments, for additional optimization. | 03-26-2009 |
20110055484 | Detecting Task Complete Dependencies Using Underlying Speculative Multi-Threading Hardware - Mechanisms are provided for tracking dependencies of threads in a multi-threaded computer program execution. The mechanisms detect a dependency of a first thread's execution on results of a second thread's execution in an execution flow of the multi-threaded computer program. The mechanisms further store, in a hardware thread dependency vector storage associated with the first thread's execution, an identifier of the dependency by setting at least one bit in the hardware thread dependency vector storage corresponding to the second thread. Moreover, the mechanisms schedule tasks performed by the multi-threaded computer program based on the hardware thread dependency vector storage to minimize squashing of threads. | 03-03-2011 |
20110219222 | Building Approximate Data Dependences with a Moving Window - Mechanisms for building approximate data dependences using a moving look-back window are provided. The mechanisms track dependence information for memory accesses over iterations of execution of a portion of code. The mechanisms receive a memory access of an iteration of the portion of code, the memory access having an address for access the memory and an access type indicating at least one of a read or a write access type. An entry in a moving look-back window data structure is generated corresponding to a memory location accessed by the memory access. The entry comprises at least an identification of the address, the access type, and an iteration number corresponding to the iteration of the memory access. The moving look-back window data structure is utilized to determine dependence information for memory accesses over a plurality of iterations of the portion of code. | 09-08-2011 |
20110320785 | Binary Rewriting in Software Instruction Cache - Mechanisms are provided for dynamically rewriting branch instructions in a portion of code. The mechanisms execute a branch instruction in the portion of code. The mechanisms determine if a target instruction of the branch instruction, to which the branch instruction branches, is present in an instruction cache associated with the processor. Moreover, the mechanisms directly branch execution of the portion of code to the target instruction in the instruction cache, without intervention from an instruction cache runtime system, in response to a determination that the target instruction is present in the instruction cache. In addition, the mechanisms redirect execution of the portion of code to the instruction cache runtime system in response to a determination that the target instruction cannot be determined to be present in the instruction cache. | 12-29-2011 |
20110320786 | Dynamically Rewriting Branch Instructions in Response to Cache Line Eviction - Mechanisms are provided for evicting cache lines from an instruction cache of the data processing system. The mechanisms store, for a portion of code in a current cache line, a linked list of call sites that directly or indirectly target the portion of code in the current cache line. A determination is made as to whether the current cache line is to be evicted from the instruction cache. The linked list of call sites is processed to identify one or more rewritten branch instructions having associated branch stubs, that either directly or indirectly target the portion of code in the current cache line. In addition, the one or more rewritten branch instructions are rewritten to restore the one or more rewritten branch instructions to an original state based on information in the associated branch stubs. | 12-29-2011 |
20110321002 | Rewriting Branch Instructions Using Branch Stubs - Mechanisms are provided for rewriting branch instructions in a portion of code. The mechanisms receive a portion of source code having an original branch instruction. The mechanisms generate a branch stub for the original branch instruction. The branch stub stores information about the original branch instruction including an original target address of the original branch instruction. Moreover, the mechanisms rewrite the original branch instruction so that a target of the rewritten branch instruction references the branch stub. In addition, the mechanisms output compiled code including the rewritten branch instruction and the branch stub for execution by a computing device. The branch stub is utilized by the computing device at runtime to determine if execution of the rewritten branch instruction can be redirected directly to a target instruction corresponding to the original target address in an instruction cache of the computing device without intervention by an instruction cache runtime system. | 12-29-2011 |
20110321021 | Arranging Binary Code Based on Call Graph Partitioning - Mechanisms are provided for arranging binary code to reduce instruction cache conflict misses. These mechanisms generate a call graph of a portion of code. Nodes and edges in the call graph are weighted to generate a weighted call graph. The weighted call graph is then partitioned according to the weights, affinities between nodes of the call graph, and the size of cache lines in an instruction cache of the data processing system, so that binary code associated with one or more subsets of nodes in the call graph are combined into individual cache lines based on the partitioning. The binary code corresponding to the partitioned call graph is then output for execution in a computing device. | 12-29-2011 |
20120198169 | Binary Rewriting in Software Instruction Cache - Mechanisms are provided for dynamically rewriting branch instructions in a portion of code. The mechanisms execute a branch instruction in the portion of code. The mechanisms determine if a target instruction of the branch instruction, to which the branch instruction branches, is present in an instruction cache associated with the processor. Moreover, the mechanisms directly branch execution of the portion of code to the target instruction in the instruction cache, without intervention from an instruction cache runtime system, in response to a determination that the target instruction is present in the instruction cache. In addition, the mechanisms redirect execution of the portion of code to the instruction cache runtime system in response to a determination that the target instruction cannot be determined to be present in the instruction cache. | 08-02-2012 |
20120198170 | Dynamically Rewriting Branch Instructions in Response to Cache Line Eviction - Mechanisms are provided for evicting cache lines from an instruction cache of the data processing system. The mechanisms store, for a portion of code in a current cache line, a linked list of call sites that directly or indirectly target the portion of code in the current cache line. A determination is made as to whether the current cache line is to be evicted from the instruction cache. The linked list of call sites is processed to identify one or more rewritten branch instructions having associated branch stubs, that either directly or indirectly target the portion of code in the current cache line. In addition, the one or more rewritten branch instructions are rewritten to restore the one or more rewritten branch instructions to an original state based on information in the associated branch stubs. | 08-02-2012 |
20120198429 | Arranging Binary Code Based on Call Graph Partitioning - Mechanisms are provided for arranging binary code to reduce instruction cache conflict misses. These mechanisms generate a call graph of a portion of code. Nodes and edges in the call graph are weighted to generate a weighted call graph. The weighted call graph is then partitioned according to the weights, affinities between nodes of the call graph, and the size of cache lines in an instruction cache of the data processing system, so that binary code associated with one or more subsets of nodes in the call graph are combined into individual cache lines based on the partitioning. The binary code corresponding to the partitioned call graph is then output for execution in a computing device. | 08-02-2012 |
20120204016 | Rewriting Branch Instructions Using Branch Stubs - Mechanisms are provided for rewriting branch instructions in a portion of code. The mechanisms receive a portion of source code having an original branch instruction. The mechanisms generate a branch stub for the original branch instruction. The branch stub stores information about the original branch instruction including an original target address of the original branch instruction. Moreover, the mechanisms rewrite the original branch instruction so that a target of the rewritten branch instruction references the branch stub. In addition, the mechanisms output compiled code including the rewritten branch instruction and the branch stub for execution by a computing device. The branch stub is utilized by the computing device at runtime to determine if execution of the rewritten branch instruction can be redirected directly to a target instruction corresponding to the original target address in an instruction cache of the computing device without intervention by an instruction cache runtime system. | 08-09-2012 |
20120246654 | Constant Time Worker Thread Allocation Via Configuration Caching - Mechanisms are provided for allocating threads for execution of a parallel region of code. A request for allocation of worker threads to execute the parallel region of code is received from a master thread. Cached thread allocation information identifying prior thread allocations that have been performed for the master thread are accessed. Worker threads are allocated to the master thread based on the cached thread allocation information. The parallel region of code is executed using the allocated worker threads. | 09-27-2012 |
20130151822 | Efficient Enqueuing of Values in SIMD Engines with Permute Unit - Mechanisms, in a data processing system having a processor, for generating enqueued data for performing computations of a conditional branch of code are provided. Mask generation logic of the processor operates to generate a mask representing a subset of iterations of a loop of the code that results in a condition of the conditional branch being satisfied. The mask is used to select data elements from an input data element vector register corresponding to the subset of iterations of the loop of the code that result in the condition of the conditional branch being satisfied. Furthermore, the selected data elements are used to perform computations of the conditional branch of code. Iterations of the loop of the code that do not result in the condition of the conditional branch being satisfied are not used as a basis for performing computations of the conditional branch of code. | 06-13-2013 |
20130283250 | Thread Specific Compiler Generated Customization of Runtime Support for Application Programming Interfaces - Mechanisms are provided for generating a customized runtime library for source code. Source code is analyzed to identify a region of code implementing an application programming interface or programming standard of interest. An invocation tree data structure is generated based on results of analysis of functions of the application programming interface or programming standard of interest that the region of code invokes. A custom runtime library is generated based on the invocation tree data structure. The custom runtime library comprises only a subset of runtime library functions, less than a total number of runtime library functions for the application programming interface or programming standard of interest, actually invoked by the region of code and does not include all runtime library functions in the total number of runtime library functions for the application programming interface or programming standard of interest. | 10-24-2013 |
20140068581 | OPTIMIZED DIVISION OF WORK AMONG PROCESSORS IN A HETEROGENEOUS PROCESSING SYSTEM - A compiler implemented by a computer performs optimized division of work across heterogeneous processors. The compiler divides source code into code sections and characterizes each of the code sections based on pre-defined criteria. Each of the code sections is characterized as at least one of: allocate to a main processor, allocate to a processing element, allocate to one of a parameterized main processor and a parameterized processing element, and indeterminate. The compiler analyzes side-effects and costs of executing the code sections on allocated processors, and transforms the code sections based on results of the analyzing. The transforming includes re-characterizing the code sections for alternate execution in a runtime environment. | 03-06-2014 |
20140068582 | OPTIMIZED DIVISION OF WORK AMONG PROCESSORS IN A HETEROGENEOUS PROCESSING SYSTEM - A compiler implemented by a computer performs optimized division of work across heterogeneous processors. The compiler divides source code into code sections and characterizes each of the code sections based on pre-defined criteria. Each of the code sections is characterized as at least one of: allocate to a main processor, allocate to a processing element, allocate to one of a parameterized main processor and a parameterized processing element, and indeterminate. The compiler analyzes side-effects and costs of executing the code sections on allocated processors, and transforms the code sections based on results of the analyzing. The transforming includes re-characterizing the code sections for alternate execution in a runtime environment. | 03-06-2014 |
20140136857 | POWER-CONSTRAINED COMPILER CODE GENERATION AND SCHEDULING OF WORK IN A HETEROGENEOUS PROCESSING SYSTEM - A heterogeneous processing system includes a compiler for performing power-constrained code generation and scheduling of work in the heterogeneous processing system. The compiler produces source code that is executable by a computer. The compiler performs a method. The method includes dividing a power budget for the heterogeneous processing system into a discrete number of power tokens. Each of the power tokens has an equal value of units of power. The method also includes determining a power requirement for executing a code segment on a processing element of the heterogeneous processing system. The determining is based on characteristics of the processing element and the code segment. The method further includes allocating, to the processing element at runtime, at least one of the power tokens to satisfy the power requirement. | 05-15-2014 |
20140136858 | POWER-CONSTRAINED COMPILER CODE GENERATION AND SCHEDULING OF WORK IN A HETEROGENEOUS PROCESSING SYSTEM - An active memory system includes a computer and an active memory device including layers of memory forming a three-dimensional memory device and individual columns of chips forming vaults in communication with a processing element and logic. The processing element is configured to communicate to the chips and other processing elements. The active memory system also includes a compiler configured to implement a method. The method includes dividing a power budget for the active memory device into a discrete number of power tokens, each of the power tokens having an equal value of units of power. The method also includes determining a power requirement for executing a code segment on the processing element of the active memory device based on characteristics of the processing element and the code segment. The method further includes allocating, to the processing element at runtime, one or more power tokens to satisfy the power requirement. | 05-15-2014 |
Patent application number | Description | Published |
20090083722 | System and Method for Stable Transitions in the Presence of Conditionals for an Advanced Dual-Representation Polyhedral Loop Transformation Framework - A system and method for stable transitions in the presence of conditionals for an advanced dual-representation polyhedral loop transformation framework are provided. The mechanisms of the illustrative embodiments address the weaknesses of the known polyhedral loop transformation based approaches by providing mechanisms for performing code generation transformations on individual statement instances in an intermediate representation generated by the polyhedral loop transformation optimization of the source code. These code generation transformations have the important property that they do not change program order of the statements in the intermediate representation. This property allows the result of the code generation transformations to be provided back to the polyhedral loop transformation mechanisms in a program statement view, via a new re-entrance path of the illustrative embodiments, for additional optimization. In addition, mechanisms are provided for ensuring code stabilization in the presence of conditions such that code bloat is not encountered during re-entrance. | 03-26-2009 |
20090083724 | System and Method for Advanced Polyhedral Loop Transformations of Source Code in a Compiler - A system and method for advanced polyhedral loop transformations of source code in a compiler are provided. The mechanisms of the illustrative embodiments address the weaknesses of the known polyhedral loop transformation based approaches by providing mechanisms for performing code generation transformations on individual statement instances in an intermediate representation generated by the polyhedral loop transformation optimization of the source code. These code generation transformations have the important property that they do not change program order of the statements in the intermediate representation. This property allows the result of the code generation transformations to be provided back to the polyhedral loop transformation mechanisms in a program statement view, via a new re-entrance path of the illustrative embodiments, for additional optimization. | 03-26-2009 |
20090307673 | System and Method for Domain Stretching for an Advanced Dual-Representation Polyhedral Loop Transformation Framework - A system and method for domain stretching for an advanced dual-representation polyhedral loop transformation framework are provided. The mechanisms of the illustrative embodiments address the weaknesses of the known polyhedral loop transformation based approaches by providing mechanisms for performing code generation transformations on individual statement instances in an intermediate representation generated by the polyhedral loop transformation optimization of the source code. These code generation transformations have the important property that they do not change program order of the statements in the intermediate representation. This property allows the result of the code generation transformations to be provided back to the polyhedral loop transformation mechanisms in a program statement view, via a new re-entrance path of the illustrative embodiments, for additional optimization. In addition, mechanisms are provided for stretching the domains of statements in a program loop view of the source code to thereby normalize the domains. | 12-10-2009 |
20120017203 | Path-Sensitive Analysis for Reducing Rollback Overheads - A mechanism is provided for path-sensitive analysis for reducing rollback overheads. The mechanism receives, in a compiler, program code to be compiled to form compiled code. The mechanism divides the code into basic blocks. The mechanism then determines a restore register set for each of the one or more basic blocks to form one or more restore register sets. The mechanism then stores the one or more register sets such that responsive to a rollback during execution of the compiled code. A rollback routine identifies a restore register set from the one or more restore register sets and restores registers identified in the identified restore register set. | 01-19-2012 |
Patent application number | Description | Published |
20080229291 | Compiler Implemented Software Cache Apparatus and Method in which Non-Aliased Explicitly Fetched Data are Excluded - A compiler implemented software cache apparatus and method in which non-aliased explicitly fetched data are excluded are provided. With the mechanisms of the illustrative embodiments, a compiler uses a forward data flow analysis to prove that there is no alias between the cached data and explicitly fetched data. Explicitly fetched data that has no alias in the cached data are excluded from the software cache. Explicitly fetched data that has aliases in the cached data are allowed to be stored in the software cache. In this way, there is no runtime overhead to maintain the correctness of the two copies of data. Moreover, the number of lines of the software cache that must be protected from eviction is decreased. This leads to a decrease in the amount of computation cycles required by the cache miss handler when evicting cache lines during cache miss handling. | 09-18-2008 |
20080282064 | System and Method for Speculative Thread Assist in a Heterogeneous Processing Environment - A system and method for speculative assistance to a thread in a heterogeneous processing environment is provided. A first set of instructions is identified in a source code representation (e.g., a source code file) that is suitable for speculative execution. The identified set of instructions are analyzed to determine the processing requirements. Based on the analysis, a processor type is identified that will be used to execute the identified first set of instructions based. The processor type is selected from more than one processor types that are included in the heterogeneous processing environment. The heterogeneous processing environment includes more than one heterogeneous processing cores in a single silicon substrate. The various processing cores can utilize different instruction set architectures (ISAs). An object code representation is then generated for the identified first set of instructions with the object code representation being adapted to execute on the determined type of processor. | 11-13-2008 |
20090055588 | Performing Useful Computations While Waiting for a Line in a System with a Software Implemented Cache - Mechanisms for performing useful computations during a software cache reload operation are provided. With the illustrative embodiments, in order to perform software caching, a compiler takes original source code, and while compiling the source code, inserts explicit cache lookup instructions into appropriate portions of the source code where cacheable variables are referenced. In addition, the compiler inserts a cache miss handler routine that is used to branch execution of the code to a cache miss handler if the cache lookup instructions result in a cache miss. The cache miss handler, prior to performing a wait operation for waiting for the data to be retrieved from the backing store, branches execution to an independent subroutine identified by a compiler. The independent subroutine is executed while the data is being retrieved from the backing store such that useful work is performed. | 02-26-2009 |
20090070753 | INCREASE THE COVERAGE OF PROFILING FEEDBACK WITH DATA FLOW ANALYSIS - The present invention provides a system and method for profiling based optimization of a computer program. The system includes an optimization module that profiles feedback from profiled part of a program to a part of the program that was not reached, an identical expressions model that identifies at least one identical expression in the program that have not been profiled and copies alias profiling result from a profiled reference to the reference that has not been profiled, a speculative identical expressions model that identifies at least one speculative identical expression in the program that have not been profiled and copies alias profiling result from a profiled speculative identical reference to the speculative identical reference that has not been profiled, and a similar expressions model that identifies at least one similar expression in the program that have not been profiled and copies alias profiling result from a similar profiled reference to the similar reference that has not been profiled. | 03-12-2009 |
Patent application number | Description | Published |
20090017195 | CURABLE ENCAPSULANT COMPOSITION AND ASSOCIATED METHOD - An encapsulant for encapsulating electronic components and a method of making and/or using the encapsulant may be provided. An electronic device that includes the encapsulant may be provided. The curable encapsulant composition may include a mixture of a functionalized polymer and at least one reactive monomer composition. The reactive monomer composition may include a reactive monomer component that may be a low temperature solid and may be present in an amount in the reactive monomer composition a range of greater than about 20 weight percent based on the total weight of reactive monomer composition. | 01-15-2009 |
20090107632 | ADHESIVE COMPOSITIONS FOR HIGH TEMPERATURE SENSORS AND METHODS OF MAKING THE SAME - An adhesive composition is provided which effectively bonds a sensor to a surface having a temperature up to approximately 250° C. The adhesive composition comprises an epoxy resin and a latent cationic cure catalyst effective to cure the epoxy resin. The invention also provides a method of preparing an adhesive composition comprising blending an epoxy resin and a latent cationic cure catalyst effective to cure the epoxy resin, wherein the composition is capable of effectively bonding a sensor to a surface having a temperature up to approximately 250° C. The invention further provides a method of bonding a sensor to a surface comprising the steps of applying an adhesive composition to a first surface of the sensor or to a surface area of an object to be monitored, the adhesive composition comprising an epoxy compound and a latent cationic cure catalyst effective to cure the epoxy resin. The first surface of the sensor is contacted with the surface area of the object whereby the adhesive composition is located therebetween, and wherein the composition effectively bonds the sensor to the object surface at a temperature up to approximately 250° C. | 04-30-2009 |
20100073167 | SECURITY TAG FOR OPTICAL MEDIA AND PROCESSES FOR FABRICATION AND ATTACHMENT - An activation system for optical media in one embodiment includes a tag having at least one pair of conductors with at least one heating element coupled to the conductors. The heating element is oriented proximate one or more activation regions on the optical media, and wherein the heating element activates the optical media. The tag in one embodiment is an elongate flexible tag material with a number of conductors that couple on one end to heating elements wherein the heating elements are disposed within a media case such that they are proximate activation regions on a media article. | 03-25-2010 |
20100113681 | Sulfur-containing cycloaliphatic compound, process for its preparation, filled sulfur-vulcanizable elastomer composition containing same and articles fabricated therefrom - A sulfur-containing cycloaliphatic compound, useful as a crosslinker for filled sulfur-vulcanizable elastomer compositions, is represented by the general formula: | 05-06-2010 |
20100154639 | LIQUID CARBON DIOXIDE ABSORBENT AND METHODS OF USING THE SAME - A carbon dioxide absorbent comprising (i) a liquid, nonaqueous silicon-based material, functionalized with one or more groups that either reversibly react with CO | 06-24-2010 |
20100158777 | CARBON DIOXIDE ABSORBENT AND METHOD OF USING THE SAME - In accordance with one aspect, the present invention provides an amino-siloxane composition comprising at least one of structures I, II, III, IV or V said compositions being useful for the capture of carbon dioxide from gas streams such as power plant flue gases. In addition, the present invention provides methods of preparing the amino-siloxane compositions are provided. Also provided are methods for reducing the amount of carbon dioxide in a process stream employing the amino-siloxane compositions of the invention as species which react with carbon dioxide to form an adduct with carbon dioxide. The reaction of the amino-siloxane compositions provided by the present invention with carbon dioxide is reversible and thus, the method provides for multicycle use of said compositions. | 06-24-2010 |
20100194574 | PARTICLE DETECTION SYSTEM AND METHOD OF DETECTING PARTICLES - A method for detecting an aerosol plume includes emitting a light beam from a light source, the light beam having at least one light pulse, wherein the light pulse having a pulse width of between about 10 picoseconds (ps) and about 75 nanoseconds (ns), detecting backscattered light produced by the at least one light pulse interacting with particles in the aerosol plume, determining a presence of the aerosol plume based on the detected backscattered light, and outputting a signal indicating the presence of the aerosol plume. | 08-05-2010 |
20110308390 | CARBON DIOXIDE ABSORBENT AND METHOD OF USING THE SAME - In accordance with one aspect, the present invention provides a composition which contains the amino-siloxane structures I, or III, as described herein. The composition is useful for the capture of carbon dioxide from process streams. In addition, the present invention provides methods of preparing the amino-siloxane composition. Another aspect of the present invention provides methods for reducing the amount of carbon dioxide in a process stream employing the amino-siloxane compositions of the invention, as species which react with carbon dioxide to form an adduct with carbon dioxide. | 12-22-2011 |
20130042475 | PANELS AND PROCESSES THEREFOR - Polymer-based materials and processes suitable for producing panels, for example, panels for use in a fan shroud abradable seal of a turbofan engine. Such a process includes introducing constituents of an expandable foam material into a continuous forming apparatus that continuously compounds the constituents into a partially-cured compounded polymeric material, which is then continuously formed with the continuous forming apparatus to produce a continuous form having a constant cross-sectional shape transverse to a continuous forming direction of the continuous forming apparatus. A portion of the continuous form is then deformed to produce a preform, and the preform is cured within a restricted volume to cause the preform to expand and produce the panel. | 02-21-2013 |
20140107289 | RUBBER COMPOSITION, METHOD FOR ITS FORMATION, AND AUTOMOTIVE TIRE CONTAINING THE COMPOSITION - A rubber composition with disperse phase particles containing poly(phenylene ether) can be formed by a method that includes melt blending an uncured rubber with a poly(phenylene ether) composition containing a poly(phenylene ether) and an oil to form an uncured rubber composition, then curing the uncured rubber composition. Before being blended with the rubber, the poly(phenylene ether) composition exhibits a glass transition temperature of about 40 to about 140° C., and during blending with the rubber, the oil component of poly(phenylene ether) composition migrates from the poly(phenylene ether) composition to the rubber, leaving a poly(phenylene ether)-containing disperse phase that gives rise to a second hysteresis peak temperature of about 160 to about 220° C. as measured by dynamic mechanical analysis of the cured rubber composition. Also described are the poly(phenylene ether) composition used in the method, a cured rubber composition formed by the method, and a tire containing the cured rubber composition. | 04-17-2014 |
20140127105 | CARBON DIOXIDE ABSORBENT AND METHOD OF USING THE SAME - In accordance with one aspect, the present invention provides a composition which contains the amino-siloxane structures I, or III, as described herein. The composition is useful for the capture of carbon dioxide from process streams. In addition, the present invention provides methods of preparing the amino-siloxane composition. Another aspect of the present invention provides methods for reducing the amount of carbon dioxide in a process stream employing the amino-siloxane compositions of the invention, as species which react with carbon dioxide to form an adduct with carbon dioxide. | 05-08-2014 |
Patent application number | Description | Published |
20080240601 | EDGE MAPPING USING PANCHROMATIC PIXELS - A method of enhancing a full-color image of a scene includes capturing an image of the scene using a two-dimensional sensor array having both color and panchromatic pixels, forming the full-color image in response to the captured color pixels, forming a reference panchromatic image in response to the captured panchromatic pixels, forming an edge map in response to the reference panchromatic image and using the edge map to enhance the full-color image. | 10-02-2008 |
20080240602 | EDGE MAPPING INCORPORATING PANCHROMATIC PIXELS - A method of enhancing a full-color image of a scene includes capturing an image of the scene using a two-dimensional sensor array having both color and panchromatic pixels, forming an edge map in response to the panchromatic pixels, forming the full-color image in response to the captured color pixels, and using the edge map to enhance the full-color image. | 10-02-2008 |
20090021810 | METHOD OF SCENE BALANCE USING PANCHROMATIC PIXELS - A method of providing an enhanced image including color and panchromatic pixels, includes using a captured image of a scene that was captured by a two-dimensional sensor array having both color and panchromatic pixels; providing an image having paxels in response to the captured image so that each paxel has color and panchromatic values; converting the paxel values to at least one luminance value and a plurality of chrominance values; and computing scene balance values from the luminance and chrominance values to be applied to an uncorrected image having color and panchromatic pixels that is either the captured image of the scene or an image derived from the captured image of the scene and using the computed scene balance values to provide an enhanced image including color and panchromatic pixels. | 01-22-2009 |
20090046182 | PIXEL ASPECT RATIO CORRECTION USING PANCHROMATIC PIXELS - A method for forming an enhanced digital full-color image having a first pixel aspect ratio includes capturing an image using an image sensor having panchromatic pixels and color pixels corresponding to at least two color photoresponses wherein color and panchromatic pixels each have a second pixel aspect ratio different from the first pixel aspect ratio, providing from the captured image a digital high-resolution panchromatic image and changing the aspect ratio of the panchromatic pixel values from the second pixel aspect ratio to the first pixel aspect ratio to produce a digital aspect corrected high-resolution panchromatic image, providing from the captured image a digital low-resolution color difference color filter array image, providing a digital aspect corrected high-resolution color difference image from the low-resolution color difference color filter array image, and using the aspect corrected high-resolution panchromatic image and an aspect corrected high-resolution color difference image to produce the enhanced digital full-color image. | 02-19-2009 |
20090051984 | IMAGE SENSOR HAVING CHECKERBOARD PATTERN - An image sensor for capturing a color image, comprising a two-dimensional array of pixels having a plurality of minimal repeating units wherein each repeating unit is composed of eight pixels having four panchromatic pixels, two pixels having the same color response, and two pixels having different color responses that are different than the pixels having the same color response, with the minimal repeating units tiled to cause each row or each column of the image sensor to have color pixels of a single color or to cause each row and each column to have color pixels of only two colors. | 02-26-2009 |
Patent application number | Description | Published |
20090075035 | PREPARING NANOPARTICLES AND CARBON NANOTUBES - Apparatus and methods for forming the apparatus include nanoparticles, catalyst nanoparticles, carbon nanotubes generated from catalyst nanoparticles, and methods of fabrication of such nanoparticles and carbon nanotubes. | 03-19-2009 |
20090269269 | COPPER OXIDE NANOPARTICLE SYSTEM - The disclosed subject matter provides a copper oxide nanoparticle, a catalyst that includes the copper oxide nanoparticle, and methods of manufacturing and using the same. The catalyst can be used to catalyze a chemical reaction (e.g., oxidizing carbon monoxide (CO) to carbon dioxide (CO | 10-29-2009 |
20090297626 | Methods for preparing metal oxides - The disclosed subject matter provides a method for preparing a metal oxide, the method includes (a) contacting a metal salt precursor with an alcohol to provide a metal oxide; and (b) removing the metal oxide from the alcohol. | 12-03-2009 |
20100135937 | METAL OXIDE NANOCRYSTALS: PREPARATION AND USES - Nanocrystalline forms of metal oxides, including binary metal oxide, perovskite type metal oxides, and complex metal oxides, including doped metal oxides, are provided. Methods of preparation of the nanocrystals are also provided. The nanocrystals, including uncapped and uncoated metal oxide nanocrystals, can be dispersed in a liquid to provide dispersions that are stable and do not precipitate over a period of time ranging from hours to months. Methods of preparation of the dispersions, and methods of use of the dispersions in forming films, are likewise provided. The films can include an organic, inorganic, or mixed organic/inorganic matrix. The films can be substantially free of all organic materials. The films can be used as coatings, or can be used as dielectric layers in a variety of electronics applications, for example as a dielectric material for an ultracapacitor, which can include a mesoporous material. Or the films can be used as a high-K dielectric in organic field-effect transistors. In various embodiments, a layered gate dielectric can include spin-cast (e.g., 8 nm-diameter) high-K BaTiO | 06-03-2010 |
20100209352 | SYNTHESIS AND CONJUGATION OF IRON OXIDE NANOPARTICLES TO ANTIBODIES FOR TARGETING SPECIFIC CELLS USING FLUORESCENCE AND MR IMAGING TECHNIQUES - The invention provides for methods for producing water-soluble iron oxide nanoparticles comprising encapsulating the nanoparticles in phospholipids micelles. Also provided are methods for conjugating the inventive nanoparticles via functionalized phospholipids to a target molecule, such as an antibody. The invention further provides methods for using the nanoparticle-antibody conjugate of the invention as a contrast agent to image specific cells or proteins in a subject using fluorescent and magnetic imaging techniques. | 08-19-2010 |
20120126199 | PREPARING NANOPARTICLES AND CARBON NANOTUBES - Apparatus and methods for forming the apparatus include nanoparticles, catalyst nanoparticles, carbon nanotubes generated from catalyst nanoparticles, and methods of fabrication of such nanoparticles and carbon nanotubes. | 05-24-2012 |
20120225006 | NANO-SIZED PARTICLES, PROCESSES OF MAKING, COMPOSITIONS AND USES THEREOF - The present invention describes methods for preparing high quality nanoparticles, i.e., metal oxide based nanoparticles of uniform size and monodispersity. The nanoparticles advantageously comprise organic alkyl chain capping groups and are stable in air and in nonpolar solvents. The methods of the invention provide a simple and reproducible procedure for forming transition metal oxide nanocrystals, with yields over 80%. The highly crystalline and monodisperse nanocrystals are obtained directly without further size selection; particle size can be easily and fractionally increased by the methods. The resulting nanoparticles can exhibit magnetic and/or optical properties. These properties result from the methods used to prepare them. Also advantageously, the nanoparticles of this invention are well suited for use in a variety of industrial applications, including cosmetic and pharmaceutical formulations and compositions. | 09-06-2012 |
20130207231 | DIELECTRIC FILM WITH NANOPARTICLES - A dielectric film is produced by applying a fluid solvent to a layer of nanoparticles and then polymerizing the solvent between the nanoparticles, or by disposing dielectric nanoparticles in a carrier fluid including a polymerizable substance, applying the resulting fluid to a substrate, and polymerizing a polymerizable substance between the nanoparticles so that the polymerizable substance solidifies to form the dielectric film including the solidified polymerizable substance and the nanoparticles between which the solidified polymerizable substance is disposed. A dielectric film can include nanoparticles and polymer material between at least some of the nanoparticles. The film can have a capacitance change of within 0%-7% over the range 20° C.-125° C. and a dielectric constant between 17.5 and 25 for the range 100 Hz-1 MHz. | 08-15-2013 |