Patent application number | Description | Published |
20090187810 | ERROR CORRECTION CODING METHOD AND DEVICE - An error correction coding method using a low-density parity-check code includes: dividing an information bit sequence to be processed for error correction coding, into (m−r) pieces of first blocks each comprising a bit sequence having a length n and r pieces of second blocks comprising respective bit sequences having lengths k | 07-23-2009 |
20100153810 | DECODING DEVICE AND RECEIVING DEVICE - A decoding apparatus for low density parity check codes includes a variable-to-check message generator and a check-to-variable message generator. The variable-to-check message generator includes a variable-to-check processing unit block, provided with an adder, and which is arranged between registers corresponding to locations of ‘1’s in a check matrix. The check-to-variable message generator includes a check-to-variable processing unit block, provided with a comparator, between registers corresponding to locations of ‘1’s in the check matrix. The decoding apparatus for low density parity check codes is simple in configuration and is able to perform high speed processing without using RAMs without the necessity of performing complex control operations. | 06-17-2010 |
20100251063 | DECODING DEVICE, DATA STORAGE DEVICE, DATA COMMUNICATION SYSTEM, AND DECODING METHOD - A data converting means generates first interim data held in one-to-one correspondence to columns vectors from data stored in a first storage means and data stored in a second storage means. A check node processing means generates second interim data for updating the data stored in the first storage means based on the sum of the first interim data and received data. The data converting means updates the data stored in the second storage means using the first interim data, and updates the data stored in the first storage means using the second interim data generated by the check node processing means. Decoded data are generated by a process carried out by the data converting means and the check node processing means. | 09-30-2010 |
20110219286 | DECODING DEVICE, DATA COMMUNICATION APPARATUS HAVING THE DECODER DEVICE, AND DATA MEMORY - A decoding device comprises two check node processing devices of feedback shift register type, each of which node processing includes a plurality of registers and a plurality of comparator circuits. A multiplexer and a demultiplexer switch between the two check node processing devices, and a memory holds the two sorts of data. The comparator circuits are interposed between registers of the check node processing device. | 09-08-2011 |
20120089884 | ERROR CORRECTION ENCODING APPARATUS, DECODING APPARATUS, ENCODING METHOD, DECODING METHOD, AND PROGRAMS THEREOF - Provided is an encoding apparatus wherein a transmission data sequence is divided into L short sequences, each of which is then encoded by use of an m-stage pseudo-cyclic low-density parity check encoding system. Each of the L encoded sequences is further divided into shorter sequences, the number of which is identical to the number m of the stages of the pseudo-cyclic codes and each of which has a length m. The shorter sequences are rearranged in order by a replacing module, thereafter encoded, by use of the m-stage pseudo-cyclic low-density parity check encoding system, and outputted. Accordingly, a decoding apparatus with a simple structure where node processing circuits (e.g., minimum-value calculating circuits), the number of which is p that is a submultiple of the number m of the foregoing stages, are provided, can be employed to efficiently decode the codes having a large frame length and a large encoding gain. | 04-12-2012 |
20130031446 | CODING DEVICE, ERROR-CORRECTION CODE CONFIGURATION METHOD, AND PROGRAM THEREOF - A coding device includes: an inspection matrix generating module that generates a block inspection matrix; and a coding module that generates and outputs a code word from an input message by the inspection matrix. The inspection matrix generating module includes: a degree-allocation unit that prescribes function values of the block inspection matrix by the coefficients of a self-reciprocal polynomial expression; a weight distribution determination unit that prescribes the number of components that are non-zero matrices among the components of each block of the block inspection matrix using a mask pattern; a first degree-altering unit that considers the sum of the components of the k_r-th row block of the block inspection matrix as a cyclic permutation matrix; and a second degree-altering unit that prescribes the row-block number of components that are non-zero matrices among the components of each row block excluding said k_r-th row block of the clock inspection matrix. | 01-31-2013 |
20130179757 | ERROR CORRECT CODING DEVICE, ERROR CORRECT CODING METHOD, AND ERROR CORRECT CODING PROGRAM - Disclosed are an encoding apparatus for a quasi-cyclic low-density parity check code for calculating r×m-bit redundant data for information data of length k×m bits (k, m and r are positive integers), and a cyclic addition apparatus including a k×m-bit shift register and exclusive OR. With information data of a length of k×m×L bits (L≦k), a length of (r×m×(L+1)+k×m) bits is calculated as redundant data by adding redundant data of a length of r×m×L bits calculated using the encoding apparatus L times, k×m-bit data calculated by inputting the information data of a length of k×m×L bits to the cyclic addition apparatus, and r×m-bit redundant data calculated by inputting the k×m-bit data to the encoding apparatus. | 07-11-2013 |
20150085960 | CARRIER WAVE REPRODUCTION DEVICE AND CARRIER WAVE REPRODUCTION METHOD - The present invention provides a carrier wave reproduction device in which bit-error characteristics are improved without decreasing transmission capacity. The carrier wave reproduction device is equipped with an interpolation filter that estimates a phase error for a received symbol on the basis of a pilot symbol included in the received symbol, a first phase rotation machine that rotates a phase of the received symbol in response to the phase error estimated by the interpolation filter and then outputs the rotated symbol as a first output symbol, a phase error compensating unit that compensates for the phase error remaining in the first output symbol and then outputs the result of the compensation as a second output symbol, a QAM symbol demapping unit that calculates both a first bit string corresponding to the first output symbol and a second bit string corresponding to the second output signal, and an error correction decoder which performs error correction on the bit error in the first bit string and outputs the result. The phase error compensating unit refers to the first bit string after error correction has been performed thereon and then compensates for the phase error remaining in the first output symbol. | 03-26-2015 |