Patent application number | Description | Published |
20100207206 | TRANSISTOR - A transistor has a cell array with two or more transistor cells, a temperature sensor, which is integrated in the cell array or is adjacent to the cell array, and an isolation structure. The isolation structure isolates the temperature sensor from the cell array, and has an isolation trench, which is arranged between the cell array and the temperature sensor. The distance between the temperature sensor and the active transistor cell that is closest to the temperature sensor corresponds approximately to the pitch between active transistor cells within the cell array. | 08-19-2010 |
20100230764 | INTEGRATED CIRCUIT HAVING FIELD EFFECT TRANSISTORS AND MANUFACTURING METHOD - An integrated circuit having field effect transistors and manufacturing method. One embodiment provides an integrated circuit including a first FET and a second FET. At least one of source, drain, gate of the first FET is electrically connected to the corresponding one of source, drain, gate of the second FET. At least one further of source, drain, gate of the first FET and the corresponding one further of source, drain, gate of the second FET are connected to a circuit element, respectively. A dopant concentration of a body along a channel of each of the first and second FETs has a peak at a peak location within the channel. | 09-16-2010 |
20110089528 | SEMICONDUCTOR HAVING OPTIMIZED INSULATION STRUCTURE AND PROCESS FOR PRODUCING THE SEMICONDUCTOR - A semiconductor having an optimized insulation structure which is simple and inexpensive to produce and can be made smaller than LOCOS insulation structures is disclosed. An implantation mask on a surface of a semiconductor substrate is used to implant elements into the semiconductor substrate, which elements, on thermal activation, form an insulation region together with the further elements of the semiconductor substrate. The thermal activation is effected by means of laser irradiation, during which the semiconductor substrate is briefly melted and then recrystallizes during the subsequent cooling, so that the implanted elements form the insulation region together with the further elements of the semiconductor substrate. | 04-21-2011 |
20110278667 | SEMICONDUCTOR COMPONENT ARRANGEMENT AND METHOD FOR PRODUCING THEREOF - A semiconductor component arrangement and method for producing thereof is disclosed. One embodiment provides at least one power semiconductor component integrated in a semiconductor body and at least one logic component integrated in the semiconductor body. The logic component includes a trench extending into the semiconductor body proceeding from a first side, at least one gate electrode arranged in the trench and insulated from the semiconductor body by a gate dielectric, and at least one source zone and at least one drain zone of a first conduction type, which are formed in the semiconductor body in a manner adjacent to the gate dielectric and in a manner spaced apart from one another in a peripheral direction of the trench and between which at least one body zone of a second conduction type is arranged. | 11-17-2011 |
20120299092 | SEMICONDUCTOR COMPONENT ARRANGEMENT AND METHOD FOR PRODUCING THEREOF - A semiconductor component arrangement and method for producing thereof is disclosed. One embodiment provides at least one power semiconductor component integrated in a semiconductor body and at least one logic component integrated in the semiconductor body. The logic component includes a trench extending into the semiconductor body proceeding from a first side, at least one gate electrode arranged in the trench and insulated from the semiconductor body by a gate dielectric, and at least one source zone and at least one drain zone of a first conduction type, which are formed in the semiconductor body in a manner adjacent to the gate dielectric and in a manner spaced apart from one another in a peripheral direction of the trench and between which at least one body zone of a second conduction type is arranged. | 11-29-2012 |
20140120673 | INTEGRATED CIRCUIT HAVING FIELD EFFECT TRANSISTORS AND MANUFACTURING METHOD - An integrated circuit having field effect transistors and manufacturing method. One embodiment provides an integrated circuit including a first FET and a second FET. At least one of source, drain, gate of the first FET is electrically connected to the corresponding one of source, drain, gate of the second FET. At least one further of source, drain, gate of the first FET and the corresponding one further of source, drain, gate of the second FET are connected to a circuit element, respectively. A dopant concentration of a body along a channel of each of the first and second FETs has a peak at a peak location within the channel. | 05-01-2014 |
20140167155 | SEMICONDUCTOR COMPONENT ARRANGEMENT AND METHOD FOR PRODUCING THEREOF - A semiconductor component arrangement and method for producing thereof is disclosed. One embodiment provides at least one power semiconductor component integrated in a semiconductor body and at least one logic component integrated in the semiconductor body. The logic component includes a trench extending into the semiconductor body proceeding from a first side, at least one gate electrode arranged in the trench and insulated from the semiconductor body by a gate dielectric, and at least one source zone and at least one drain zone of a first conduction type, which are formed in the semiconductor body in a manner adjacent to the gate dielectric and in a manner spaced apart from one another in a peripheral direction of the trench and between which at least one body zone of a second conduction type is arranged. | 06-19-2014 |
20160056280 | Minority Carrier Conversion Structure - According to an embodiment of a semiconductor device, the semiconductor device includes a power device well in a semiconductor substrate, a logic device well in the substrate and spaced apart from the power device well by a separation region of the substrate, and a minority carrier conversion structure including a first doped region of a first conductivity type in the separation region, a second doped region of a second conductivity type in the separation region and a conducting layer connecting the first and second doped regions. The second doped region includes a first part interposed between the first doped region and the power device well and a second part interposed between the first doped region and the logic device well. | 02-25-2016 |