Patent application number | Description | Published |
20090271553 | METHOD AND APPARATUS FOR OBTAINING TRACE INFORMATION OF MULTIPLE PROCESSORS ON AN SOC USING A SEGMENTED TRACE RING BUS TO ENABLE A FLEXIBLE TRACE OUTPUT CONFIGURATION - An integrated bus architecture for transmitting trace information from a plurality of processors included on an integrated chip having one or more peripheral I/O channels comprises a segmented bus having a plurality of segments arranged in a ring topology and configured to transmit trace information in a circular pathway from upstream segments to downstream segments, and one or more trace output circuits each connected to a respective segment and each including a switch configured to be dynamically toggled between enabled and disabled states. The plurality of segments includes a respective segment for each processor having a coupling unit connected to a trace port of the processor. The coupling unit is configured to receive trace information from the trace port, to receive trace information from the adjacent upstream segment, and to transmit items of trace information to the adjacent downstream segment. Each trace output circuit is configured to transmit trace information to a respective peripheral I/O channel when in the enabled state. Each trace output circuit is configured to transmit trace information to the adjacent downstream segment when in the disabled state. | 10-29-2009 |
20120141118 | ARBITRATION OF OPTICAL COMMUNICATION BUS - A method, bus controller, and computer program product for arbitrating use of a communication bus for a certain one of a plurality of interconnected nodes that share the bus. The method includes the steps of: presenting a data frame on the transmitter and receiver side of the bus, where the certain node presents at the transmitter side, where the data frame has a embedded clock of a predetermined timing and a header field, synchronizing, by the certain node, with the embedded clock in the data frame at the receiving side of the bus, successively presenting, by the certain node, an idle pattern on the bus determined by a preassigned node ID, emitting light, by the certain node, on the bus at a predetermined timing preassigned to the certain node, and monitoring light emission on the bus that indicates a bus access request from another one of the nodes. | 06-07-2012 |
20140071785 | INTEGRITY CHECK OF MEASURED SIGNAL TRACE DATA - A method of monitoring signals is disclosed, wherein a plurality of command signals and address signals are consecutively expressed, as a measurement target. The method includes setting a strobe timing that has a predetermined initial value; calculating an error rate by monitoring the plurality of command signals, in accordance with the strobe timing; monitoring the plurality of address signals, and calculating a burst rate from a difference between the consecutive plurality of address signals, in accordance with the strobe timing; identifying timing where the calculated error rate and calculated burst rate are both optimized; and in the event the timing where both the calculated error rate and calculated burst rate are optimized cannot be identified, altering a predetermined value of the set strobe timing, and repeating the calculating, monitoring, and identifying. | 03-13-2014 |
20140075250 | INTEGRITY CHECK OF MEASURED SIGNAL TRACE DATA - A method of monitoring signals is disclosed, wherein a plurality of command signals and address signals are consecutively expressed, as a measurement target. The method includes setting a strobe timing that has a predetermined initial value; calculating an error rate by monitoring the plurality of command signals, in accordance with the strobe timing; monitoring the plurality of address signals, and calculating a burst rate from a difference between the consecutive plurality of address signals, in accordance with the strobe timing; identifying timing where the calculated error rate and calculated burst rate are both optimized; and in the event the timing where both the calculated error rate and calculated burst rate are optimized cannot be identified, altering a predetermined value of the set strobe timing, and repeating the calculating, monitoring, and identifying. | 03-13-2014 |
20150331795 | MEMORY ACCESS TRACING METHOD - A method for identifying, in a system including two or more computing devices that are able to communicate with each other, with each computing device having with a cache and connected to a corresponding memory, a computing device accessing one of the memories, includes monitoring memory access to any of the memories; monitoring cache coherency commands between computing devices; and identifying the computing device accessing one of the memories by using information related to the memory access and cache coherency commands. | 11-19-2015 |
20150331797 | MEMORY ACCESS TRACING METHOD - A method for identifying, in a system including two or more computing devices that are able to communicate with each other, with each computing device having with a cache and connected to a corresponding memory, a computing device accessing one of the memories, includes monitoring memory access to any of the memories; monitoring cache coherency commands between computing devices; and identifying the computing device accessing one of the memories by using information related to the memory access and cache coherency commands. | 11-19-2015 |
20150363311 | MEMORY MANAGEMENT METHOD - A method for managing main memory including DRAM and NVRAM in a computer depending on the operation state of the computer is provided. The method includes: (a) upon start of the computer, loading a program and the like into the DRAM, and loading predetermined read-only data and the like into the NVRAM; (b) in a state transition from a normal operation to a suspend state, moving data in the DRAM to the NVRAM; (c) in a state transition from the suspend state to the normal operation, reading data from the NVRAM for program execution; (d) in the case where a data write to the NVRAM occurs, stopping the data write, and moving data in a data area of the NVRAM subjected to the data write, to the DRAM; and (e) performing the data write to the DRAM to which the data has been moved. | 12-17-2015 |
20160049831 | POWER TRANSMITTING DEVICE, POWER RECEIVING DEVICE, POWER SUPPLY SYSTEM, AND POWER SUPPLY METHOD - Provided are a power transmitting device, a power receiving device, a power supply system, and a power supply method able to supply electric power by emitting electromagnetic waves. A power transmitting device ( | 02-18-2016 |