Patent application number | Description | Published |
20090116301 | INTERNAL DATA COMPARISON FOR MEMORY TESTING - Memory devices having a normal mode of operation and a test mode of operation are useful in quality programs. The test mode of operation includes a data comparison test mode. The data comparison test mode systematically searches for addresses of defective columns by comparing a sensed data value to an expected data value at various levels of decoding. Upon detection of a defective column, the address value for each level of decoding is stored and can be used in redundancy selection to replace the defective columns with redundant columns. The comparison is internal to the memory device such that the test mode is independent of external testers and can be run after fabrication, even by an end user, thus allowing repair after fabrication and installation. The comparisons are facilitated by compare logic inserted into the data path. | 05-07-2009 |
20090238006 | ADJUSTING PROGRAMMING OR ERASE VOLTAGE PULSES IN RESPONSE TO THE NUMBER OF PROGRAMMING OR ERASE FAILURES - Memory devices and methods of operating memory devices are provided. In one such embodiment a programming voltage pulse or an erase voltage pulse is applied to memory cells of a memory device. A number of the memory cells that failed to program or erase is determined and is compared to a certain number that can be different than a number of memory cells to be programmed or erased. The programming voltage pulse or the erase voltage pulse is adjusted in response to the comparison of the number of memory cells that failed to program or erase to the certain number. The adjusted programming voltage pulse or the adjusted erase voltage pulse is applied to the memory cells that failed to program or erase. | 09-24-2009 |
20100046295 | FAST DATA ACCESS MODE IN A MEMORY DEVICE - A fast data access circuit that has both a standard clock mode and a fast data access mode. The mode is selectable through a mode/configuration register. A configuration word loaded into the register has bits to indicate the desired mode and the input clock frequency. In the fast data access mode, a clock delay circuit uses the clock frequency setting bits to select a delay to be added to the input clock. The higher the clock frequency, the less the added delay. The delayed clock generates FIFO control signals to control a data FIFO register. During the fast data access mode, the data is output from the data FIFO register at a faster rate than in the standard clock mode. | 02-25-2010 |
20100054041 | ADJUSTING PROGRAMMING OR ERASE VOLTAGE PULSES IN RESPONSE TO A RATE OF PROGRAMMING OR ERASING - Memory devices and methods of operating memory devices are provided. In one such embodiment, a programming voltage pulse or an erase voltage pulse is applied to memory cells of a memory device. A rate at which programming or erasing is proceeding is determined. The programming voltage pulse or the erase voltage pulse is adjusted at least partially in response to the determined rate. The adjusted programming voltage pulse or the adjusted erase voltage pulse is applied to the memory cells that failed to program or erase. | 03-04-2010 |
20100211733 | DATA VALID INDICATION METHOD AND APPARATUS - Memory devices and methods facilitate handling of data received by a memory device through the use of data grouping and assignment of data validity status values to grouped data. For example, data is received and delineated into one or more data groups and a data validity status is associated with each data group. Data groups having a valid status are latched into one or more cache registers for storage in an array of memory cells wherein data groups comprising an invalid status are rejected by the one or more cache registers. | 08-19-2010 |
20100235679 | DEFECTIVE MEMORY BLOCK REMAPPING METHOD AND SYSTEM, AND MEMORY DEVICE AND PROCESSOR-BASED SYSTEM USING SAME - A non-volatile memory device includes a block remapping system that offsets an input block address by the addresses of non-functional blocks to provide an output block address that is used to address the memory device. The system generates the output block addresses by, in effect, adding to the input block address the addresses of all non-functional blocks of memory that are between an initial address and the output block address. The system performs this function be comparing the input block address to the address of any defective block. If the address of the defective block is less than or equal to the input block address, the addresses of all defective blocks starting at the block address are added to the input block address. The system then iteratively performs this process using each output block address generated by the system in place of the input block address. | 09-16-2010 |
20110219260 | DEFECTIVE MEMORY BLOCK REMAPPING METHOD AND SYSTEM, AND MEMORY DEVICE AND PROCESSOR-BASED SYSTEM USING SAME - A non-volatile memory device includes a block remapping system that offsets an input block address by the addresses of non-functional blocks to provide an output block address that is used to address the memory device. The system generates the output block addresses by, in effect, adding to the input block address the addresses of all non-functional blocks of memory that are between an initial address and the output block address. The system performs this function be comparing the input block address to the address of any defective block. If the address of the defective block is less than or equal to the input block address, the addresses of all defective blocks starting at the block address are added to the input block address. The system then iteratively performs this process using each output block address generated by the system in place of the input block address. | 09-08-2011 |
20110310675 | LOCAL SENSING IN A MEMORY DEVICE - Methods for sensing, memory devices, and memory systems are disclosed. In one such memory device, a local sense circuit provides sensing of an upper group of memory cells while a global sense circuit provides sensing of a lower group of memory cells. Data sensed by the local sense circuit is transferred to the global sense circuit over local data lines or a global transfer line that is multiplexed to the local data lines. An alternate embodiment uses the local sense circuit to sense both upper and lower groups of memory cells. | 12-22-2011 |
20120230110 | METHOD AND APPARATUS FOR ADDRESSING MEMORY ARRAYS - The present description relates to non-volatile memory arrays and the operation thereof In at least one embodiment, the non-volatile memory array may include a plurality of memory modules coupled in a daisy chain with enable in/out signals, and a single chip enable signal coupled in parallel to each memory module. With such a configuration, all memory units within each of the memory modules of each memory array may be addressed with the single chip enable | 09-13-2012 |
20120311297 | LOGICAL UNIT ADDRESS ASSIGNMENT - Described embodiments include logical units within a memory device with control circuitry configured to assign a logical unit address to the logical unit. Apparatus including a plurality of the logical units arranged in a daisy chain configuration and methods of assigning logical unit addresses to the logical units are also disclosed. | 12-06-2012 |
20130003465 | LOCAL SENSING IN A MEMORY DEVICE - Methods for sensing, memory devices, and memory systems are disclosed. In one such memory device, a local sense circuit provides sensing of an upper group of memory cells while a global sense circuit provides sensing of a lower group of memory cells. Data sensed by the local sense circuit is transferred to the global sense circuit over local data lines or a global transfer line that is multiplexed to the local data lines. An alternate embodiment uses the local sense circuit to sense both upper and lower groups of memory cells. | 01-03-2013 |
20140068186 | METHODS AND APPARATUS FOR DESIGNATING OR USING DATA STATUS INDICATORS - Memory devices and methods facilitate handling of data received by a memory device through the use of data grouping and assignment of data validity status values to grouped data. For example, data is received and delineated into one or more data groups and a data validity status is associated with each data group. Data groups having a valid status are latched into one or more cache registers for storage in an array of memory cells wherein data groups comprising an invalid status are rejected by the one or more cache registers. | 03-06-2014 |
20140293704 | Auto-Suspend and Auto-Resume Operations for a Multi-Die NAND Memory Device - A method and apparatus that controls a peak-current condition in a multi-die memory, such as a solid-state drive, by determining by at least one die of the multi-die memory whether a subsequent memory operation is a high-current memory operation, such as an operation to enable a charge pump of the die, an operation to charge a bit line of the die, or a program/erase loop operation, or a combination thereof. The die enters a suspended-operation mode if the subsequent memory operation is determined to be a high current memory operation. Operation is resumed by the die in response to a resume operation event, such as, but not limited to, a command specifically address to the die, an indication from another die that a high-current memory operation is complete. Once operation is resumed, the die performs the high-current memory operation. | 10-02-2014 |
Patent application number | Description | Published |
20090300237 | ASYNCHRONOUS/SYNCHRONOUS INTERFACE - The present disclosure includes methods, and circuits, for operating a memory device. One method embodiment for operating a memory device includes controlling data transfer through a memory interface in an asynchronous mode by writing data to the memory device at least partially in response to a write enable signal on a first interface contact, and reading data from the memory device at least partially in response to a read enable signal on a second interface contact. The method further includes controlling data transfer in a synchronous mode by transferring data at least partially in response to a clock signal on the first interface contact, and providing a bidirectional data strobe signal on an interface contact not utilized in the asynchronous mode. | 12-03-2009 |
20110029751 | ENHANCED BLOCK COPY - The present disclosure includes methods and apparatus for an enhanced block copy. One embodiment includes reading data from a source block located in a first portion of the memory device, and programming the data to a target block located in a second portion of the memory device. The first and second portions are communicatively coupled by data lines extending across the portions. The data lines are communicatively uncoupled between the first and second portions for at least one of the reading and programming acts. | 02-03-2011 |
20110182128 | ASYNCHRONOUS/SYNCHRONOUS INTERFACE - The present disclosure includes methods, and circuits, for operating a memory device. One method embodiment for operating a memory device includes controlling data transfer through a memory interface in an asynchronous mode by writing data to the memory device at least partially in response to a write enable signal on a first interface contact, and reading data from the memory device at least partially in response to a read enable signal on a second interface contact. The method further includes controlling data transfer in a synchronous mode by transferring data at least partially in response to a clock signal on the first interface contact, and providing a bidirectional data strobe signal on an interface contact not utilized in the asynchronous mode. | 07-28-2011 |
20120314517 | ASYNCHRONOUS/SYNCHRONOUS INTERFACE - The present disclosure includes methods, and circuits, for operating a memory device. One method embodiment for operating a memory device includes controlling data transfer through a memory interface in an asynchronous mode by writing data to the memory device at least partially in response to a write enable signal on a first interface contact, and reading data from the memory device at least partially in response to a read enable signal on a second interface contact. The method further includes controlling data transfer in a synchronous mode by transferring data at least partially in response to a clock signal on the first interface contact, and providing a bidirectional data strobe signal on an interface contact not utilized in the asynchronous mode. | 12-13-2012 |
20130304984 | ENHANCED BLOCK COPY - The present disclosure includes methods and apparatus for an enhanced block copy. One embodiment includes reading data from a source block located in a first portion of the memory device, and programming the data to a target block located in a second portion of the memory device. The first and second portions are communicatively coupled by data lines extending across the portions. The data lines are communicatively uncoupled between the first and second portions for at least one of the reading and programming acts. | 11-14-2013 |
20140153335 | ASYNCHRONOUS/SYNCHRONOUS INTERFACE - The present disclosure includes methods, and circuits, for operating a memory device. One method embodiment for operating a memory device includes controlling data transfer through a memory interface in an asynchronous mode by writing data to the memory device at least partially in response to a write enable signal on a first interface contact, and reading data from the memory device at least partially in response to a read enable signal on a second interface contact. The method further includes controlling data transfer in a synchronous mode by transferring data at least partially in response to a clock signal on the first interface contact, and providing a bidirectional data strobe signal on an interface contact not utilized in the asynchronous mode. | 06-05-2014 |
20140258619 | APPARATUSES AND METHODS FOR A MEMORY DIE ARCHITECTURE - Apparatuses and methods for reducing capacitance on a data bus are disclosed herein. In accordance with one or more described embodiments, an apparatus may comprise a plurality of memories coupled to an internal data bus and a command and address bus, each of the memories configured to receive a command on the command and address bus. One of the plurality of memories may be coupled to an external data bus. The one of the plurality of memories may be configured to provide program data to the internal data bus when the command comprises a program command and another of the plurality of memories is a target memory of the program command and may be configured to provide read data to the external data bus when the command comprises a read command and the another of the plurality of memories is a target memory of the read command. | 09-11-2014 |