# Ning Lu

## Ning Lu, Essex Junction, VT US

Patent application number | Description | Published |
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20090030663 | SYSTEM AND METHOD FOR MODELING STOCHASTIC BEHAVIOR OF A SYSTEM OF N SIMILAR STATISTICAL VARIABLES - A system and method for modeling stochastic behavior of a system of N similar statistical variables using N uncorrelated/independent random model parameters. More particularly, a system and method of modeling device across chip variations and device mismatch. The method includes modeling stochastic behavior of a system of N similar statistical variables using N uncorrelated/independent random model parameters. The method includes providing a system of N similar statistical variables, wherein each stochastic variable has a same standard deviation. The method further includes partially correlating each and every pair of stochastic variables among N variables, wherein a degree of partial correlation is a same for all pairs of variables. A statistical model is constructed to represent a system of N stochastic variables in which only N independent stochastic model parameters are used. A one-to-one mapping relation exists between N model parameters and the N variables. The method further includes finding unique values of the N model parameters given a set of values of the N variables. Reversely, the method also includes finding the values of the N variables given a set of values of the N model parameters. | 01-29-2009 |

20090204365 | MODELING SPATIAL CORRELATIONS - Modeling spatial correlations of semiconductor characteristic variations is disclosed. In one embodiment, a method includes developing a solution for each of a plurality of specific forms of spatial correlations of a characteristic of a circuit design and developing a plurality of solution methods for a given spatial correlation; selecting one of the solutions that is closest to a desired spatial correlation; and modeling the desired spatial correlation using the selected solution. | 08-13-2009 |

20110093242 | Method and System for Constructing Corner Models for Multiple Performance Targets - A method, system and article of manufacture are disclosed for constructing corner models for multiple performance targets for circuit simulations. The method includes identifying N (N≧2) device and/or circuit performance targets F | 04-21-2011 |

20110213587 | METHOD AND COMPUTER PROGRAM PRODUCT FOR FINDING STATISTICAL BOUNDS, CORRESPONDING PARAMETER CORNERS, AND A PROBABILITY DENSITY FUNCTION OF A PERFORMANCE TARGET FOR A CIRCUIT - Disclosed are embodiments of a method and an associated computer program product for finding the statistical bounds, the corresponding parameter corners and the probability density function of one or more performance targets for a circuit without requiring Monte Carlo simulation runs. To accomplish this, a joint probability density function for independent parameters that affect the performance target can be constructed. Then, based on the joint probability density function, the statistical bounds of the performance target can be found by constructing an equal-probability-density surface of the joint probability density function and solving a constrained optimization problem on that equal-probability-density surface. Once the statistical bounds are determined, the corresponding parameter corners for the performance target can also be determined. After obtaining multiple statistical bounds corresponding to different accumulated probability density, the probability density function of the performance target can also be obtained. | 09-01-2011 |

20120035892 | METHOD AND SYSTEM OF DEVELOPING CORNER MODELS FOR VARIOUS CLASSES ON NONLINEAR SYSTEMS - A method, system and article of manufacture are disclosed for developing corner models for various classes of nonlinear systems. The method comprises the steps of determining whether an explicit relationship between one or more performance targets vs. statistical model parameters is known; and deciding, when an explicit relationship between one or more performance targets vs. statistical model parameters is known, whether the relationship is linear or nonlinear. The relationship is constructed in the fractional form when an explicit relationship between one or more performance targets vs. statistical model parameters is not known. In one embodiment, the invention provides an optimal corner model solution for a single performance target, which varies with statistical parameters nonlinearly. In another embodiment, the invention provides an optimal and common corner model solution for multiple performance targets which vary with statistical model parameters nonlinearly. A step of decreasing the order of a target function on statistical model parameters may be used in the process of generating corner models. | 02-09-2012 |

20120124530 | MAKING A DISCRETE SPATIAL CORRELATION CONTINUOUS - A mechanism is provided for making a discrete spatial correlation on a 2D grid continuous. The region has given grid points and each of the grid points has its discrete stochastic variable. Additional grid points and associated stochastic variables are established on the boundary and corners of the region. All correlation coefficients are obtained among the given discrete stochastic variables and the additional discrete stochastic variables. For each of two given spatial points whose spatial correlation is needed, a quadrilateral containing it is identified by four grid points, and a stochastic variable for it is expressed as a weighted linear combination of four stochastic variables at four grid points, with four weights being a continuous function of the coordinate of the point. The resulting spatial correlation is a weighted linear combination of multiple discrete correlation coefficients each weight being a continuous function of the coordinates of the two given points. | 05-17-2012 |

20120126792 | STRUCTURES AND METHODS FOR RF DE-EMBEDDING - Electrical structures, methods, and computer program products for radio frequency (RF) de-embedding are provided. A structure includes a first test device, a first through structure corresponding to the first test device, and a first open structure corresponding to the first test device. The structure also includes a second test device having at least one different physical dimension than the first test device but otherwise identical to the first test device, a second through structure corresponding to the second test device, and a second open structure corresponding to the second test device. A method includes determining a first electrical parameter of the first test device in a first DUT structure and a second electrical parameter of the second test device in a second DUT structure based on measured electrical parameters of the first and the second DUT structures, through structures, and open structures. | 05-24-2012 |

20120212877 | CAPACITOR STRUCTURE - The disclosure relates generally to capacitor structures and more particularly, to capacitor structures having interdigitated metal fingers. Metal finger capacitors may have at least one layer, the at least one layer including: a first set of fingers, wherein each finger of the first set includes an end integrally connected to a bus segment of a first bus; a second set of fingers interdigitated with the first set of fingers, wherein each finger of the second set includes an end integrally connected to a bus segment of a second bus; an in port integrally connected to the first bus and an out port integrally connected to the second bus; and wherein a width of the first and second bus is non-uniform across a length of the first and second bus. | 08-23-2012 |

20120226456 | METHOD OF CALCULATING FET GATE RESISTANCE - A method and device determine FET gate resistance based on both polysilicon resistance and the resistance values of wires and contacts connected to the gate node, plus the fraction of the electric current in each wire segment and in each contact and the path length of electric current in polysilicon. A new gate resistance expression (i.e., a master equation) is used for total gate resistance, which is the sum of core gate resistance and the resistance of wires and contacts connecting polysilicon and a gate node. When there are two or more paths for electric current going from polysilicon to the gate node, the total resistance also depends on the direction and path length of electric current in polysilicon, and the method and device next determine the fraction of electric current in each path by minimizing total resistance with respect to the fractions of the electric current in each path. | 09-06-2012 |

20120227020 | METHOD OF DETERMINING FET SOURCE/DRAIN WIRE, CONTACT, AND DIFFUSION RESISTANCES IN THE PRESENCE OF MULTIPLE CONTACTS - A method calculates a total source/drain resistance for a field effect transistor (FET) device. The method counts the number (N) of contacts in each source/drain region of the FET device, partitions each source/drain region into N contact regions and calculates a set of resistances of elements and connections to the FET device. The measured dimensions of widths, lengths, and distances of layout shapes forming the FET and the connections to the FET are determined and a set of weights based on relative widths of the contact regions are computed. The total source/drain resistance of the FET device is determined by summing products of the set of resistances and the set of weights for each of a plurality of contacts in series, the summing being performed for all of the plurality of contacts in one of a source region and a drain region of the FET. A netlist is formed based on the total source resistance and total drain resistance of the FET device. | 09-06-2012 |

20120254820 | METHOD, A PROGRAM STORAGE DEVICE AND A COMPUTER SYSTEM FOR MODELING THE TOTAL CONTACT RESISTANCE OF A SEMICONDUCTOR DEVICE HAVING A MULTI-FINGER GATE STRUCTURE - Disclosed are embodiments for modeling contact resistance of devices, such as metal oxide semiconductor field effect transistors or varactors, that specifically have a multi-finger gate structure. In the embodiments, a set of expressions for total contact resistance are presented, in which (i) the total contact resistance is the sum of the resistance contribution from the contact (or the set of all contacts) in each diffusion region, (ii) the resistance contribution from the contact (or the set of all contacts) to the total contact resistance is the product of its resistance and the square of the relative electric current passing through it, and (iii) the electric current passing through the contact (or the set of all contacts) in a shared diffusion region (i.e., in an inner diffusion region) is twice of the electric current passing through the contact (or the set of all contacts) in an unshared diffusion region (i.e., in an outer diffusion region). | 10-04-2012 |

20120311518 | METHOD, A SYSTEM AND A PROGRAM STORAGE DEVICE FOR MODELING THE RESISTANCE OF A MULTI-CONTACTED DIFFUSION REGION - Disclosed are embodiments of a method and program storage device for modeling the resistance of a multi-contacted diffusion region of a semiconductor device, such as a metal oxide semiconductor field effect transistor (MOSFET), a metal oxide semiconductor capacitor (MOS capacitor), a bipolar transistor, etc. The embodiments provide a formula for determining the total parasitic resistance (R | 12-06-2012 |

20120326270 | INTERDIGITATED VERTICAL NATIVE CAPACITOR - A metal capacitor structure includes a plurality of line level structures vertically interconnected with via level structures. Each first line level structure and each second line level structure includes a set of parallel metal lines that is physically joined at an end to a rectangular tab structure having a rectangular horizontal cross-sectional area. A first set of parallel metal lines within a first line level structure and a second set of parallel metal lines within a second line level structure are interdigitated and parallel to each other, and can collectively form an interdigitated uniform pitch structure. Because the rectangular tab structures do not protrude toward each other within a region between two facing sidewalls of the rectangular tab structures, sub-resolution assist features (SRAFs) can be employed to provide a uniform width and a uniform pitch throughout the entirety of the interdigitated uniform pitch structure. | 12-27-2012 |

20130007686 | METHOD, SYSTEM AND PROGRAM STORAGE DEVICE FOR MODELING THE CAPACITANCE ASSOCIATED WITH A DIFFUSION REGION OF A SILICON-ON-INSULATOR DEVICE - Disclosed are embodiments of a method, system and program storage device for accurately modeling parasitic capacitance(s) associated with a diffusion region of a silicon-on-insulator (SOI) device and doing so based, at least in part, on proximity to adjacent conductive structures. In these embodiments, the layout of an integrated circuit design can be analyzed to determine, for the diffusion region, shape, dimension and proximity information. Then, a formula can be developed and used for determining the parasitic capacitance between the diffusion region and the substrate below (C | 01-03-2013 |

20130024828 | SOLUTIONS FOR NETLIST REDUCTION FOR MULTI-FINGER DEVICES - A computer-implemented method for performing a layout extraction for a multi-fingered semiconductor device is disclosed. The method reduces the netlist for the device and the number of device fingers by identifying a set of device common nodes, and combining a plurality of parasitic elements in the device to form a set of representative parasitic elements which are connected to respective device common nodes. In one embodiment, the method includes: extracting a netlist for the multi-finger device which includes a plurality of parasitic elements identifying a set of common nodes; replacing the fingers of the multi-finger device with a new device having a width equivalent to the widths of the fingers of the multi-finger device; and combining the parasitic elements of at least one device common node into a single representative parasitic element which is representative of the original parasitic elements. | 01-24-2013 |

20130174109 | DEVICE MISMATCH CORNER MODEL - A device mismatch corner model for semiconductor device simulation is provided. A method of providing the device mismatch corner model for semiconductor device simulation, includes selecting a type of electric performance target F for a type of device, determining a number N of semiconductor devices for which mismatches among electric performance targets of the semiconductor devices are simulated, and determining a desired k-sigma mismatch corner value among N(N−1)/2 pairs of the electric performance targets. The method further includes identifying at least one electric parameter P of the semiconductor devices that has a mismatch component and contributes to the mismatches among the electric performance targets of the semiconductor devices, determining a plurality of corner values for the at least one electrical parameter P, and running at most N circuit simulations based on the determined plurality of corner values which are recalculated for each of the circuit simulations. | 07-04-2013 |

20130179127 | METHOD OF MODELING SPATIAL CORRELATIONS AMONG INTEGRATED CIRCUITS WITH RANDOMLY GENERATED SPATIAL FREQUENCIES - A computer-implemented method, computer system, and computer program for modeling spatial correlations among a set of devices. A method includes: assigning a set of physical coordinates to each device in the set of devices; representing one of a process parameter or an electric parameter for each device as a sum of at least two stochastic terms, wherein the at least two stochastic terms are chosen to satisfy the spatial correlations; simulating formation of the set of devices using the physical coordinates and the at least one of the process parameter or the electric parameter; and obtaining statistical properties of the set of devices from the simulation. | 07-11-2013 |

20130289964 | MODELING THE TOTAL PARASITIC RESISTANCES OF THE SOURCE/DRAIN REGIONS OF A MULTI-FIN MULTI-GATE FIELD EFFECT TRANSISTOR - In the embodiments, a full resistive network is used to determine resistance contributions to the total parasitic resistance of each source/drain region of a multi-fin multi-gate field effect transistor (MUGFET). These resistance contributions include: a first resistance contribution of end portions of the fins, which are connected in pseudo-parallel by a local interconnect; second resistance contributions of segments of the local interconnect, which are connected in pseudo-series; and any other resistance contributions of any other resistive elements between the end portions of the fins and a single resistive element through which all the diffusion region current flows. The multi-fin MUGFET is then represented in a netlist as a simple field effect transistor with the total parasitic resistances represented as single resistive elements connected to the source/drain nodes of that field effect transistor. This simplified netlist is then used to simulate performance of the multi-fin MUGFET. | 10-31-2013 |

20130297277 | MODELING GATE RESISTANCE OF A MULTI-FIN MULTI-GATE FIELD EFFECT TRANSISTOR - The embodiments relate to modeling resistance in a multi-fin multi-gate field effect transistor (MUGFET). In these embodiments, a design for a multi-fin MUGFET comprises a gate structure with a horizontal portion traversing multiple semiconductor fins and comprising a plurality of first resistive elements connected in series, with vertical portions adjacent to opposing sides of the semiconductor fins and comprising second resistive elements connected in parallel by the horizontal portion, and with contact(s) comprising third resistive element(s). The total gate resistance is determined based on resistance contributions from the first resistive elements, the second resistive elements and the third resistive element(s), particularly, where each resistive contribution is based on a resistance value of the resistive element, a first fraction of current from the semiconductor fins entering the resistive element and a second fraction of the current from the semiconductor fins exiting the resistive element. | 11-07-2013 |

20140103434 | MULTI-FINGER TRANSISTOR LAYOUT FOR REDUCING CROSS-FINGER ELECTRIC VARIATIONS AND FOR FULLY UTILIZING AVAILABLE BREAKDOWN VOLTAGES - Structure and methods for a semiconductor transistor design. The transistor structure comprises a field effect transistor having a multi-finger gate and three or more diffusion regions. Each diffusion region is identified as either a source region or a drain region, and each diffusion region is further identified as either an inner diffusion region or an outer diffusion region. Electrical contacts are established in the inner diffusion regions and the outer diffusion regions. There are approximately twice as many contacts in an inner source region as in the outer source region. There are approximately twice as many contacts in an inner drain region as in the outer drain region. The number and locations of contacts in each diffusion region are adjusted to reduce the difference among source node voltages of all fingers and the difference among drain node voltages of all fingers. | 04-17-2014 |

20140117453 | LOCAL INTERCONNECTS FOR FIELD EFFECT TRANSISTOR DEVICES - A multi-field effect transistor (FET) device includes a first FET device arranged on a substrate, the first FET device including a first active region and a second active region, a second FET device arranged on the substrate, the second FET device including a first active region and a second active region, and a first conductive interconnect electrically connecting the first active region of the first FET device to the first active region of the second FET device, the first conductive interconnect having a first cross sectional area proximate to the first active region of the first FET device that is greater than a second cross sectional area proximate to the first active region of the second FET device. | 05-01-2014 |

20150057980 | STRUCTURES AND METHODS FOR RF DE-EMBEDDING - Electrical structures, methods, and computer program products for radio frequency (RF) de-embedding are provided. A structure includes a first test device, a first through structure corresponding to the first test device, and a first open structure corresponding to the first test device. The structure also includes a second test device having at least one different physical dimension than the first test device but otherwise identical to the first test device, a second through structure corresponding to the second test device, and a second open structure corresponding to the second test device. A method includes determining a first electrical parameter of the first test device in a first DUT structure and a second electrical parameter of the second test device in a second DUT structure based on measured electrical parameters of the first and the second DUT structures, through structures, and open structures. | 02-26-2015 |

20150089464 | SYSTEM AND METHOD FOR GENERATING A FIELD EFFECT TRANSISTOR CORNER MODEL - Disclosed are a system, method and computer program product for generating a field effect transistor (FET) corner model for a performance target (e.g., delay) that accurately preserves partial correlations among involved statistical model parameters (e.g., channel lengths, threshold voltages, overlap capacitance, etc.) of different types of field effect transistors within an integrated circuit. To accomplish this, an initial simulation run is performed to determine a nominal performance value with all statistical model parameters set at their nominal values. Then, multiple additional simulation runs are performed to determine corner performance values. In each successive additional simulation run, statistical model parameters of the different types of field effect transistors are offset from their nominal model parameters values in correlated ways. Then, based on performance differences between each of the corner performance values and the nominal performance value, a standard deviation for the performance target is determined. | 03-26-2015 |

## Ning Lu, Pleasanton, CA US

Patent application number | Description | Published |
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20090197262 | BORDETELLA DETECTION ASSAY - Disclosed herein are methods and compositions for detecting | 08-06-2009 |

20140170638 | HAV detection - Methods for detecting HAV in a biological sample are provided, comprising amplifying a target nucleic acid comprising the sequence of HAV in a reaction mixture. The reaction mixture comprises a biological sample which may contain the target nucleic acid and set of oligonucleotides. The invention also provides kits for the detection of HAV. | 06-19-2014 |

## Ning Lu, Folsom, CA US

Patent application number | Description | Published |
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20090146853 | Scalable context adaptive binary arithmetic coding - One embodiment of the invention concerns performing renormalization in content adaptive binary arithmetic coding (CABAC) only after multiple bins are processed. | 06-11-2009 |

20090167775 | MOTION ESTIMATION COMPATIBLE WITH MULTIPLE STANDARDS - A motion estimation engine may be implemented to support multiple video encoding standards. The motion estimation engine may be designed to support two macroblock partitioning modes: one for frame type video signals and the other for mixed frame-field type video signals. Additionally, the motion estimation engine provides the mixing unidirectional option (forward/backward) and the mixing bidirectional option. Furthermore, the motion estimation engine may use a unified 4-tap interpolation filter for fractional macroblock search during motion estimation. | 07-02-2009 |

20090168871 | Video motion estimation - In accordance with some embodiments of the present invention, distortion may be calculated using hardware for purposes of motion estimation. The distortion may be determined in the frequency domain. In some embodiments, a modified Haar wavelet transform may be utilized. The penalty in terms of the number of motion vectors may be determined for each location to achieve better distortion in some embodiments. A look up table may be utilized to determine an acceptable penalty. In some cases, the user can input information about an acceptable penalty. | 07-02-2009 |

20090168881 | CONFIGURABLE MOTION ESTIMATION - In some embodiments, a motion estimation method and engine are provided. | 07-02-2009 |

20090168883 | CONFIGURABLE PERFORMANCE MOTION ESTIMATION FOR VIDEO ENCODING - A motion estimation engine may be implemented to include a skip checking module, an integer search module, a macroblock partitioning module, a fractional search module, a bidirectional motion estimation refinement module, and an intra search module. The motion estimation engine may perform fractional search/bidirectional motion estimation refinement and intra search in parallel. Additionally, modules in the motion estimation engine may be partially or fully turned on or off to accommodate different motion estimation requirements. Furthermore, the motion estimation engine may implement early exit strategy to further save computation. | 07-02-2009 |

## Ning Lu, Chappaqua, NY US

Patent application number | Description | Published |
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20110152083 | NETWORK COPOLYMER CROSSLINKED COMPOSITIONS AND PRODUCTS COMPRISING THE SAME - The present invention provides for a household, agricultural, coating or personal care product composition containing the crosslinked reaction product of a network composition the reaction product of: (i) at least one anionic polymerizable ethylenically unsaturated monomer (I) selected from the group consisting of | 06-23-2011 |

20110152423 | NETWORK COPOLYMER CROSSLINKED EMULSIONS AND DEMULSIFYING COMPOSITIONS COMPRISING THE SAME - The present invention is directed to a network composition the reaction product of: (i) at least one anionic polymerizable ethylenically unsaturated monomer (I) selected from the group consisting of | 06-23-2011 |

20110152444 | NETWORK COPOLYMER CROSSLINKED COMPOSITIONS AND METHODS OF MAKING THE SAME - The present invention is directed to a network composition having the reaction product of: (i) at least one anionic polymerizable ethylenically unsaturated monomer (I) selected from the group consisting of | 06-23-2011 |

20130121948 | Association product of amino functional hydrophobic polymers with hydrophilic polymers containing acid groups, methods of preparation, and applications for employing the same - There is provided herein a composition comprising the non-covalent bonded reaction product of a hydrophilic polymer containing an acid functional group and a hydrophobic polymer which contains an amine group bound directly to the hydrophobic polymer backbone; and, optionally a diluent, as well as a process of making such a composition. | 05-16-2013 |

20130123529 | Block ABA silicone polyalkyleneoxide copolymers, methods of preparation, and applications for employing the same - There is provided herein a linear tri-block copolymer having the average formula (1): | 05-16-2013 |

## Ning Lu, Richland, WA US

Patent application number | Description | Published |
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20110270452 | SCHEDULING AND MODELING THE OPERATION OF CONTROLLABLE AND NON-CONTROLLABLE ELECTRONIC DEVICES - Disclosed herein are representative embodiments of methods, apparatus, and systems for controlling and scheduling power distribution in a power network, such as household power network. One disclosed embodiment is a system comprising a central controller and a control device coupled to a household appliance. The central controller can comprise computing hardware coupled to a wireless transceiver. The central controller can be configured to generate and transmit control signals for controlling the operational state of the household appliance according to the schedule. Furthermore, the control device can be configured to receive the transmitted control signals from the central controller and to control the operational state of the household appliance in response to the control signals. | 11-03-2011 |

20120119579 | CONTROLLER FOR HYBRID ENERGY STORAGE - A controller is disclosed for hybrid systems providing power to an electrical power grid. The controller reduces wear on hybrid systems by having only a fast unit tuned to track fluctuations of a regulation signal in a normal mode of operation. By contrast, the slow unit does not track fluctuations in the regulation signal in the normal mode of operation, which reduces wear on the slow unit. The normal mode of operation is defined by an energy range of the fast unit. Energy band parameters associated with the energy range can be dynamically modified in order to optimize the efficiency of the hybrid system. | 05-17-2012 |

20130282181 | CONTROLLER FOR THERMOSTATICALLY CONTROLLED LOADS - A system and method of controlling aggregated thermostatically controlled appliances (TCAs) for demand response is disclosed. A targeted load profile is formulated and a forecasted load profile is generated. The TCAs within an “on” or “off” control group are prioritized based on their operating temperatures. The “on” or “off” status of the TCAs is determined. Command signals are sent to turn on or turn off the TCAs. | 10-24-2013 |

## Ning Lu, Saratoga, CA US

Patent application number | Description | Published |
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20120063506 | TECHNIQUES ENABLING VIDEO SLICE ALIGNMENT FOR LOW-LATECY VIDEO TRANSMISSIONS OVER MMWAVE COMMUNICATIONS - An embodiment of the present invention provides an apparatus, comprising, a transceiver adapted for low-latency video transmissions over mmWave communications by using a slice alignment indication field in an audio/video protocol adaptation layer (A/V PAL) packet header to indicate whether a payload is aligned at a slice boundary and thus does not need parsing at a sink. | 03-15-2012 |

20120257104 | Detecting Video Formats - The format of telecined video may be determined including a bottom field first cadence. In addition, video using 2:3:3:2 top field first can be identified. Moreover, mixed cadence videos can also be detected. In some embodiments, mixed cadence videos may be detected by calculating variances of different areas within a frame. | 10-11-2012 |

20130170543 | SYSTEMS, METHODS, AND COMPUTER PROGRAM PRODUCTS FOR STREAMING OUT OF DATA FOR VIDEO TRANSCODING AND OTHER APPLICATIONS - Methods, systems, and computer program products that use descriptive information in a coded video stream to accelerate the transcoding process. This information, including information that is sometimes known as syntax information, may reside explicitly in headers of a coded stream. Examples of such information may include motion vectors, macroblock types, intra block prediction modes, inter block descriptive information, and quantization parameters. Other descriptive information may be derived from the actual coded macroblocks, e.g., the number of bits used to encode a macroblock, or the number of non-zero coefficients used in encoding, or the coefficients themselves. Such descriptive information may be used directly in the encoding phase of the transcoding process to improve the speed and throughput of the transcoding. Such descriptive information may also be used to enhance other video processing applications, such as scene change detection, determining object segmentation, or motion censoring. | 07-04-2013 |

20130251040 | Motion Estimation Compatible with Multiple Standards - A motion estimation engine may be implemented to support multiple video encoding standards. The motion estimation engine may be designed to support two macroblock partitioning modes: one for frame type video signals and the other for mixed frame-field type video signals. Additionally, the motion estimation engine provides the mixing unidirectional option (forward/backward) and the mixing bidirectional option. Furthermore, the motion estimation engine may use a unified 4-tap interpolation filter for fractional macroblock search during motion estimation. | 09-26-2013 |

20130266072 | SYSTEMS, METHODS, AND COMPUTER PROGRAM PRODUCTS FOR A VIDEO ENCODING PIPELINE - Methods, systems and computer program products that may improve the efficiency of the video encoding process. Mode decision processing and bit stream packing may be performed in parallel for various frames in a sequence. This reduces the amount of idle time for both the mode decision processing logic and the bit stream packing logic, improving the overall efficiency of the video encoder. | 10-10-2013 |

20130266080 | SYSTEMS, METHODS AND COMPUTER PROGRAM PRODUCTS FOR INTEGRATED POST-PROCESSING AND PRE-PROCESSING IN VIDEO TRANSCODING - Methods, systems and computer program products to increase the efficiency of a trancoding system by providing additional data from a video processor to an encoder, and by providing control signals from the encoder back to the video processor. The video processor may provide variances to the encoder, where these values would not otherwise be available to the encoder or would be computationally intensive for the encoder to generate on its own. The encoder may then use these variances to generate encoded, compressed video data more efficiently. The encoder may also generate control signals for use by the video processor, enabling the video processor to adapt to reconfigurations of the encoder, thereby improving the efficiency of the transcoding operation. | 10-10-2013 |

20130272392 | PROGRAM PRODUCTS FOR ITERATIVE QUANTIZATION RATE CONTROL IN VIDEO ENCODING - Iterative video encoding systems, methods and computer program products, where residue quantization and data packing operations of an encoding process may he repeated with various values for a quantization parameter, without repeating the determination of macroblock prediction code. In an embodiment, the size of an actual file generated by encoding is compared to a target file size. The QP may be adjusted depending on the amount by which these file sizes differ. The quantization and packing may then be repeated with the adjusted QP. In an embodiment, a greater difference in these file sizes results in a greater adjustment to the QP. | 10-17-2013 |

20140007115 | MULTI-MODAL BEHAVIOR AWARENESS FOR HUMAN NATURAL COMMAND CONTROL | 01-02-2014 |

20140007224 | REAL HUMAN DETECTION AND CONFIRMATION IN PERSONAL CREDENTIAL VERIFICATION | 01-02-2014 |

20140086338 | SYSTEMS AND METHODS FOR INTEGRATED METADATA INSERTION IN A VIDEO ENCODING SYSTEM - Systems and methods for the insertion of metadata in a video encoding system, without software intervention. Header data may be provided to hardware circuitry, which may then construct and format one or more headers to accommodate the header data. The header data may then be appended to the encoded video. The combination of the header data and the encoded video may then be multiplexed with audio data and/or user data, and encrypted if necessary. | 03-27-2014 |

20140219354 | METHODS, SYSTEMS, AND COMPUTER PROGRAM PRODUCTS FOR ASSESSING A MACROBLOCK CANDIDATE FOR CONVERSION TO A SKIPPED MACROBLOCK - A sequence of encoded data associated with a block of video is assessed to determine if: quantized coefficients of transformed residual pixel data associated with the block are equal to zero, the block was encoded using a temporal compression process, a slice that includes the block is configured to be encoded using only one reference picture list or two reference picture lists, the block is unpartitioned or was encoded in direct mode, a reference picture used to encode the block is the reference picture associated with a lowest index value on the one reference picture list, and an actual motion vector associated with the block is equal to a predicted motion vector associated with the block. | 08-07-2014 |

20140294314 | HIERARCHICAL IMAGE AND VIDEO CODEC - A hierarchical system and method of encoding and compressing image data, or video data including a sequence of images. In one embodiment, a line buffer is used to hold a line of an image, and as the second line of the image is read from the input data stream, 2×2 blocks of the image are transformed, e.g., by a Hadamard transform. Each transform results in a low-frequency component and three high-frequency component. The high-frequency components are encoded, e.g., using entropy coding, and sent out to the output bit stream. The low-frequency components are pushed to the line buffer. This process is continued until enough low-frequency components have been formed to complete a 2×2 block of low-frequency components, which is then transformed. The process may be repeated hierarchically for multiple layers. | 10-02-2014 |

20150039779 | CONTENT ADAPTIVE HIGH PRECISION MACROBLOCK RATE CONTROL - Methods and systems may include an apparatus having hardware logic to allocate a set of macroblock bit budgets for a bitstream associated with a video signal. The hardware logic can also control a frame size of the bitstream based on the set of macroblock bit budgets in a single pass encode configuration. In one example, the hardware logic adjusts one or more quantization parameters of the bitstream according to the set of macroblock bit budgets. | 02-05-2015 |

20150062202 | TEMPORAL DITHERING TECHNIQUE USED IN ACCUMULATIVE DATA COMPRESSION - A method of accumulating data by a processor in a nonvolatile memory to track use of a device. The method includes: retrieving by the processor a next datum for accumulation into a first accumulation stored in the memory, the next datum representing a next use of the device; generating by the processor a next dither offset; adding by the processor the next dither offset to the next datum to produce a first sum; dividing by the processor the first sum by a scale factor to produce a quantized datum; and adding by the processor the quantized datum to the first accumulation. The first accumulation tracks the use of the device. | 03-05-2015 |

## Ning Lu, Shanghai CN

Patent application number | Description | Published |
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20130249617 | LEVEL SHIFT CIRCUIT - Provided is a level shift circuit which includes: a first level shift module; a first signal input terminal for providing a first input signal for the first level shift module; a first signal output terminal for providing output from the first level shift module; a second level shift module; a second signal input terminal for providing a second input signal for the second level shift module; a second signal output terminal for providing output from the second level shift module; a drive module connected to the first signal output terminal and the second signal output terminal; and a drive signal output terminal from the drive module. The level shift circuit of the present invention can be applicable for the requirements of BCD process and prevent damages to the high-voltage device due to the excessively high gate voltage. | 09-26-2013 |