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Newhart

Manfred A. Newhart, Long Beach, CA US

Patent application numberDescriptionPublished
20080288945METHOD AND SYSTEM FOR ANALYZING INTERRELATED PROGRAMS - A method for analyzing a program having a budget, an implementation schedule and a deployment plan includes: (a) in no particular order: (1) providing a digital representation of the budget including first entries; (2) providing a digital representation of the schedule including second entries having a first relation with the first entries; and (3) providing a digital representation of the deployment plan including third entries having at least one second relation with at least one of the first and second entries; (b) establishing an expression embodying the first and second relations; (c) exercising the expression to alter at least one altered entry of the selected first second and third entries; and (d) observing at least one entry of the selected first second and third entries other than the at least one altered entry.11-20-2008

Ronald E. Newhart, Essex Junction, VT US

Patent application numberDescriptionPublished
20080252308Power Grid Structure to Optimize Performance of a Multiple Core Processor - A reduced number of voltage regulator modules provides a reduced number of supply voltages to the package. The package includes a voltage plane for each of the voltage regulator modules. Each core or other component on the die is tied to a switch on the package, and each switch is electrically connected to all of the voltage planes. A wafer-level test determines a voltage that optimizes performance of each core or other component. Given these voltage values, an engineer may determine voltage settings for the voltage regulator modules and which cores are to be connected to which voltage regulator modules. A database stores voltage setting data, such as the optimal voltage for each component, switch values, or voltage settings for each voltage regulator module. An engineering wire may permanently set each switch to customize the voltage supply to each core or other component.10-16-2008
20100153956Multicore Processor And Method Of Use That Configures Core Functions Based On Executing Instructions - A multiprocessor system having plural heterogeneous processing units schedules instruction sets for execution on a selected of the processing units by matching workload processing characteristics of processing units and the instruction sets. To establish an instruction set's processing characteristics, the homogeneous instruction set is executed on each of the plural processing units with one or more performance metrics tracked at each of the processing units to determine which processing unit most efficiently executes the instruction set. Instruction set workload processing characteristics are stored for reference in scheduling subsequent execution of the instruction set.06-17-2010

Ronald Edward Newhart, Essex Junction, VT US

Patent application numberDescriptionPublished
20080234955Uniform Power Density Across Processor Cores at Burn-In - A computer implemented method, data processing system, and computer usable code are provided for burn-in testing of a multiprocessor. A process identifies a power management data set for a plurality of processor cores associated with the multiprocessor. The process selects one or more of the plurality of processor cores to form a selected set of processor cores based upon the power management data set. The process initiates a burn-in test across the selected set of processor cores. In response to a determination that all processor cores in the plurality of processor cores have not been selected, the process repeats the above selecting and initiating steps until all the processor cores have been selected.09-25-2008
20090164399Method for Autonomic Workload Distribution on a Multicore Processor - A multiprocessor system which includes automatic workload distribution. As threads execute in the multiprocessor system, an operating system or hypervisor continuously learns the execution characteristics of the threads and saves the information in thread-specific control blocks. The execution characteristics are used to generate thread performance data. As the thread executes, the operating system continuously uses the performance data to steer the thread to a core that will execute the workload most efficiently.06-25-2009
20100049963Multicore Processor and Method of Use That Adapts Core Functions Based on Workload Execution - A processor has multiple cores with each core having an associated function to support processor operations. The functions performed by the cores are selectively altered to improve processor operations by balancing the resources applied for each function. For example, each core comprises a field programmable array that is selectively and dynamically programmed to perform a function, such as a floating point function or a fixed point function, based on the number of operations that use each function. As another example, a processor is built with a greater number of cores than can be simultaneously powered, each core associated with a function, so that cores having functions with lower utilization are selectively powered down.02-25-2010
20130013903Multicore Processor and Method of Use That Adapts Core Functions Based on Workload Execution - A processor has multiple cores with each core having an associated function to support processor operations. The functions performed by the cores are selectively altered to improve processor operations by balancing the resources applied for each function. For example, each core comprises a field programmable array that is selectively and dynamically programmed to perform a function, such as a floating point function or a fixed point function, based on the number of operations that use each function. As another example, a processor is built with a greater number of cores than can be simultaneously powered, each core associated with a function, so that cores having functions with lower utilization are selectively powered down.01-10-2013

Patent applications by Ronald Edward Newhart, Essex Junction, VT US

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