Patent application number | Description | Published |
20090061604 | GERMANIUM SUBSTRATE-TYPE MATERIALS AND APPROACH THEREFOR - Germanium circuit-type structures are facilitated. In one example embodiment, a multi-step growth and anneal process is implemented to grow Germanium (Ge) containing material, such as heteroepitaxial-Germanium, on a substrate including Silicon (Si) or Silicon-containing material. In certain applications, defects are generally confined near a Silicon/Germanium interface, with defect threading to an upper surface of the Germanium containing material generally being inhibited. These approaches are applicable to a variety of devices including Germanium MOS capacitors, pMOSFETs and optoelectronic devices. | 03-05-2009 |
20100159678 | GERMANIUM SUBSTRATE-TYPE MATERIALS AND APPROACH THEREFOR - Germanium circuit-type structures are facilitated. In one example embodiment, a multi-step growth and anneal process is implemented to grow Germanium (Ge) containing material, such as heteroepitaxial-Germanium, on a substrate including Silicon (Si) or Silicon-containing material. In certain applications, defects are generally confined near a Silicon/Germanium interface, with defect threading to an upper surface of the Germanium containing material generally being inhibited. These approaches are applicable to a variety of devices including Germanium MOS capacitors, pMOSFETs and optoelectronic devices. | 06-24-2010 |
Patent application number | Description | Published |
20120112280 | BUTTED SOI JUNCTION ISOLATION STRUCTURES AND DEVICES AND METHOD OF FABRICATION - A structure, a FET, a method of making the structure and of making the FET. The structure including: a silicon layer on a buried oxide (BOX) layer of a silicon-on-insulator substrate; a trench in the silicon layer extending from a top surface of the silicon layer into the silicon layer, the trench not extending to the BOX layer, a doped region in the silicon layer between and abutting the BOX layer and a bottom of the trench, the first doped region doped to a first dopant concentration; a first epitaxial layer, doped to a second dopant concentration, in a bottom of the trench; a second epitaxial layer, doped to a third dopant concentration, on the first epitaxial layer in the trench; and wherein the third dopant concentration is greater than the first and second dopant concentrations and the first dopant concentration is greater than the second dopant concentration. | 05-10-2012 |
20130015580 | REPLACEMENT METAL GATE STRUCTURE AND METHODS OF MANUFACTUREAANM JAIN; SAMEER HAACI BeaconAAST NYAACO USAAGP JAIN; SAMEER H Beacon NY USAANM Johnson; Jeffrey B.AACI Essex JunctionAAST VTAACO USAAGP Johnson; Jeffrey B. Essex Junction VT USAANM Li; YingAACI NewburghAAST NYAACO USAAGP Li; Ying Newburgh NY USAANM Nayfeh; Hasan M.AACI PoughkeepsieAAST NYAACO USAAGP Nayfeh; Hasan M. Poughkeepsie NY USAANM Ramachandran; RavikumarAACI PleasantvilleAAST NYAACO USAAGP Ramachandran; Ravikumar Pleasantville NY US - A replacement metal gate structure and methods of manufacturing the same is provided. The method includes forming at least one trench structure and forming a liner of high-k dielectric material in the at least one trench structure. The method further includes adjusting a height of the liner of high-k dielectric material. The method further includes forming at least one workfunction metal over the liner, and forming a metal gate structure in the at least one trench structure, over the at least one workfunction metal and the liner of high-k dielectric material. | 01-17-2013 |
20140203359 | BUTTED SOI JUNCTION ISOLATION STRUCTURES AND DEVICES AND METHOD OF FABRICATION - A structure, a FET, a method of making the structure and of making the FET. The structure including: a silicon layer on a buried oxide (BOX) layer of a silicon-on-insulator substrate; a trench in the silicon layer extending from a top surface of the silicon layer into the silicon layer, the trench not extending to the BOX layer, a doped region in the silicon layer between and abutting the BOX layer and a bottom of the trench, the first doped region doped to a first dopant concentration; a first epitaxial layer, doped to a second dopant concentration, in a bottom of the trench; a second epitaxial layer, doped to a third dopant concentration, on the first epitaxial layer in the trench; and wherein the third dopant concentration is greater than the first and second dopant concentrations and the first dopant concentration is greater than the second dopant concentration. | 07-24-2014 |
Patent application number | Description | Published |
20100330763 | METHOD OF CREATING ASYMMETRIC FIELD-EFFECT-TRANSISTORS - The present invention provides a method of forming asymmetric field-effect-transistors. The method includes forming at least a first and a second gate-mask stack on top of a semiconductor substrate, wherein the first and second gate-mask stacks include at least, respectively, a first and a second gate conductor of a first and a second transistor and have, respectively, a top surface, a first side, and a second side with the second side being opposite to the first side; performing a first halo implantation from the first side of the first and second gate-mask stacks at a first angle while applying the first gate-mask stack in preventing the first halo implantation from reaching a first source/drain region of the second transistor, wherein the first angle is equal to or larger than a predetermined value; and performing a second halo implantation from the second side of the first and second gate-mask stacks at a second angle, thereby creating halo implant in a second source/drain region of the second transistor, wherein the first and second angles are measured against a normal to the substrate. | 12-30-2010 |
20110089499 | STRUCTURE AND METHOD FOR MANUFACTURING ASYMMETRIC DEVICES - A plurality of gate structures are formed on a substrate. Each of the gate structures includes a first gate electrode and source and drain regions. The first gate electrode is removed from each of the gate structures. A first photoresist is applied to block gate structures having source regions in a source-down direction. A first halo implantation is performed in gate structures having source regions in a source-up direction at a first angle. The first photoresist is removed. A second photoresist is applied to block gate structures having source regions in a source-up direction. A second halo implantation is performed in gate structures having source regions in a source-down direction at a second angle. The second photoresist is removed. Replacement gate electrodes are formed in each of the gate structures. | 04-21-2011 |
20110254059 | STRUCTURE AND METHOD FOR MANUFACTURING ASYMMETRIC DEVICES - A plurality of gate structures are formed on a substrate. Each of the gate structures includes a first gate electrode and source and drain regions. The first gate electrode is removed from each of the gate structures. A first photoresist is applied to block gate structures having source regions in a source-down direction. A first halo implantation is performed in gate structures having source regions in a source-up direction at a first angle. The first photoresist is removed. A second photoresist is applied to block gate structures having source regions in a source-up direction. A second halo implantation is performed in gate structures having source regions in a source-down direction at a second angle. The second photoresist is removed. Replacement gate electrodes are formed in each of the gate structures. | 10-20-2011 |
20120217585 | Structure and Method for Manufacturing Asymmetric Devices - A plurality of gate structures are formed on a substrate. Each of the gate structures includes a first gate electrode and source and drain regions. The first gate electrode is removed from each of the gate structures. A first photoresist is applied to block gate structures having source regions in a source-down direction. A first halo implantation is performed in gate structures having source regions in a source-up direction at a first angle. The first photoresist is removed. A second photoresist is applied to block gate structures having source regions in a source-up direction. A second halo implantation is performed in gate structures having source regions in a source-down direction at a second angle. The second photoresist is removed. Replacement gate electrodes are formed in each of the gate structures. | 08-30-2012 |
Patent application number | Description | Published |
20120293271 | Voltage tunable oscillator using bilayer graphene and a lead zirconate titanate capacitor - A voltage controlled oscillator comprising a substrate and a bilayer graphene transistor formed on the substrate. The transistor has two signal terminals and a gate terminal positioned in between the signal terminals. A voltage controlled PZT or MEMS capacitor is also formed on the substrate. The capacitor is electrically connected to the transistor gate terminal. At least one component is connected to the transistor and capacitor to form a resonant circuit. | 11-22-2012 |
20120298960 | Hetero-Junction Tunneling Transistor - A hetero-junction tunneling transistor having a first layer of p++ silicon germanium which forms a source for the transistor at one end. A second layer of n+ silicon material is deposited so that a portion of the second layer overlies the first layer and forms the drain for the transistor. An insulating layer and metallic gate for the transistor is deposited on top of the second layer so that the gate is aligned with the overlying portions of the first and second layers. The gate voltage controls the conduction between the source and the drain and the conduction between the first and second layers occurs by vertical tunneling between the layers. | 11-29-2012 |
20120305891 | GRAPHENE CHANNEL TRANSISTORS AND METHOD FOR PRODUCING SAME - Embodiments of graphene channel transistors and methods for producing same are provided herein. In some embodiments, a graphene channel transistor may include a substrate a having a source region, a drain region, and a dielectric material disposed between the source and drain regions; a channel region comprising a graphene layer disposed atop the dielectric material and partially atop the source and drain regions; and a composite gate electrode comprising an insulator layer disposed atop the graphene layer and a conductive layer disposed atop the insulator layer. | 12-06-2012 |
20140252415 | HIGH MOBILITY, THIN FILM TRANSISTORS USING SEMICONDUCTOR/INSULATOR TRANSITION-METALDICHALCOGENIDE BASED INTERFACES - Electronic devices and methods of forming an electronic device are disclosed herein. An electronic device may include a first 2D atomic crystal layer; a second 2D atomic crystal layer disposed atop the first 2D atomic crystal layer; and an interface comprising van-der-Waals bonds between the first 2D atomic crystal layer and the second 2D atomic crystal layer. A method of forming an electronic device may include depositing a first 2D atomic crystal layer; and depositing a second 2D atomic crystal layer atop the first 2D atomic crystal layer; wherein an interface is formed between the first 2D atomic crystal layer and the second 2D atomic crystal layer via van-der-Waals bonding. | 09-11-2014 |
Patent application number | Description | Published |
20090273878 | GAS BEARING ELECTROSTATIC CHUCK - An electrostatic clamp is provided having a clamping plate, wherein the clamping plate has a central region and an annulus region. A plurality of gas supply orifices are defined in the central region of the clamping plate, wherein the plurality of gas supply orifices are in fluid communication with a pressurized gas supply, and wherein the pressurized gas supply is configured to provide a cushion of gas between the clamping surface and the workpiece in the central region of the clamping plate via the plurality of gas supply orifices. One or more gas return orifices defined in one or more of the central region and annulus region of the clamping plate, wherein the one or more gas return orifices are in fluid communication with a vacuum source, therein generally defining an exhaust path for the cushion of gas. A seal is disposed in the annulus region of the clamping plate, wherein the seal is configured to generally prevent a leakage of the cushion of gas from the central region to an environment external to the annulus region. One or more electrodes are further electrically connected to a first voltage potential to provide a first clamping force. | 11-05-2009 |
20130074564 | TAPERED STRUCTURE CONSTRUCTION - Feeding stock used to form a tapered structure into a curving device such that each point on the stock undergoes rotational motion about a peak location of the tapered structure; and the stock meets a predecessor portion of stock along one or more adjacent edges. | 03-28-2013 |
20130261400 | Instrument Port For Minimally Invasive Cardiac Surgery - The instrument ports for introducing instruments into a surgical site that are disclosed herein include a port body having a channel running therethrough from a proximal end to a distal end, an instrument sleeve in slidable contact with the channel, creating a gap therebetween, and a fluid flow element for removing emboli efficiently from the instrument port, wherein the fluid flow element includes the gap. Disclosed fluid flow systems are for use in the disclosed instrument ports. Methods are also disclosed for removably securing an instrument sleeve to a port body by anchoring the instrument port to heart tissue, making at least one flood line in a channel, flushing out emboli, and performing surgery with the instrument port. | 10-03-2013 |
20130264494 | ARRANGEMENT OF RETICLE POSITIONING DEVICE FOR ACTINIC INSPECTION OF EUV RETICLES - A reticle positioning apparatus for actinic EUV reticle inspection including a sealed inspection chamber containing a reticle stage for holding a reticle. The reticle stage has a. magnetically suspended upper stage with a long travel in a “y” direction and a magnetically suspended lower stage with a long travel in an “x” direction; and a cable stage chamber isolated from the inspection chamber by a cable chamber wall. The cable stage chamber has a cable stage movable in the “y” direction; and a tube connected at one end to the reticle stage and to the cable stage at the other end, The tube passes from the cable stage through the inspection chamber through a seal in the chamber wail and opening into the cable entry chamber for entry of cables and hoses within the cable stage chamber, which cables and hoses pass through the tube to the reticle stage. | 10-10-2013 |
20130293865 | Linear Stage for Reflective Electron Beam Lithography - A linear stacked stage suitable for REBL may include a first upper fast stage configured to translate a first plurality of wafers in a first direction along a first axis, the first upper fast stage configured to secure a first plurality of wafers; a second upper fast stage configured to translate a second plurality of wafers in a second direction along the first axis, the second upper fast stage configured to secure the second plurality of wafers, the second direction opposite to the first direction, wherein the translation of the first upper fast stage and the translation of the second upper fast stage are configured to substantially eliminate inertial reaction forces generated by motion of the first upper fast stage and the second upper fast stage; and a carrier stage configured to translate the first and second upper fast stages along a second axis. | 11-07-2013 |
20130342827 | Linear Stage and Metrology Architecture for Reflective Electron Beam Lithography - A stage metrology suitable for REBL includes an interferometer stage metrology system configured to measure the position and rotation of a short-stroke wafer scanning stage, wherein the interferometer metrology system includes two or more interferometers for each axis of measurement, wherein a first interferometer mirror is disposed on a first surface of the short-stroke wafer scanning stage and a second interferometer mirror is disposed on a second surface of the short-stroke wafer scanning stage, and a control system configured to determine a shape error for the first interferometer mirror using two or more interferometer measurements from the two or more interferometers associated with the first interferometer mirror and a shape error for the second interferometer mirror using two or more interferometer measurements from the two or more interferometers associated with the second interferometer mirror. | 12-26-2013 |
Patent application number | Description | Published |
20110013164 | Shear-Layer Chuck for Lithographic Apparatus - A lithographic apparatus is described that comprises a support structure ( | 01-20-2011 |
20120026474 | Reticle Cooling in a Lithographic Apparatus - An apparatus and method reduce temperature variation across a reticle so as to reduce the expansion variation of the reticle. One method for realizing reduced temperature variation is to fill an inner space with backfill gas under pressure, using distribution trenches and walls (e.g., flow restriction dams), rather than providing uniform backfill gas pressure across the entire reticle. In another method, the perimeter of inner space can be chosen to reduce the expansion variation across the reticle based on the functional relationship between expansion and temperature for the reticle material. In an optional or alternative approach, reduced temperature variation across the reticle can be obtained by selectively filling cavities in the interior of the fluid cooled chuck with backfill gas. | 02-02-2012 |
20140016110 | Shear-Layer Chuck for Lithographic Apparatus - A lithographic apparatus is described that comprises a support structure to hold an object. The object may be a patterning device or a substrate to be exposed. The support structure comprises a chuck, on which the object is supported, and an array of shear-compliant elongated elements normal to the chuck and the stage, such that first ends of the elongated elements contact a surface of the chuck and second ends of the elongated elements contact a stage. Through using the array of elongated elements, a transfer of stress between the stage and the chuck is substantially uniform, resulting in minimization of slippage of the object relative to the surface of the chuck during a deformation of the chuck due to the stress. | 01-16-2014 |
20140233009 | Shear-Layer Chuck for Lithographic Apparatus - A lithographic apparatus is described that comprises a support structure to hold an object. The object may be a patterning device or a substrate to be exposed. The support structure comprises a chuck, on which the object is supported, and an array of shear-compliant elongated elements normal to the chuck and the stage, such that first ends of the elongated elements contact a surface of the chuck and second ends of the elongated elements contact a stage. Through using the array of elongated elements, a transfer of stress between the stage and the chuck is substantially uniform, resulting in minimization of slippage of the object relative to the surface of the chuck during a deformation of the chuck due to the stress. | 08-21-2014 |
Patent application number | Description | Published |
20080245930 | HIGH INTENSITY LASER POWER BEAMING RECEIVER FOR SPACE AND TERRESTRIAL APPLICATIONS - Systems and methods are described that facilitate refueling a vehicle with electrical energy by targeting receiver thereon and pointing a high-intensity laser source at the receiver. Vertical multi-junction (VMJ) photocells receive the laser energy and convert the laser energy into electrical energy. The laser source can operate at a range of output power levels depending on the vehicle's energy needs. The laser source can be pulsed or continuous near-infrared laser source. A heat exchanger can be coupled to the receiver to dissipate laser energy not converted into electrical energy. If the vehicle has a propeller, the heat exchanger can be mounted to the vehicle in the propeller wash path. | 10-09-2008 |
20090171477 | LASER GENERATED SYNTHETIC MEGA SCALE APERTURE FOR SOLAR ENERGY CONCENTRATION AND HARNESSING - Systems and methods are described that employ high-intensity lasers to set up a thin plasma sheet, also called a waveguide or “hot shell”, in the atmosphere as a function of beam intensity and geometry. A laser beam can be spread and directed with physical optics (e.g., lenses, mirrors, other optical elements, etc.) to generate a thin inverted cone-shaped hot shell waveguide in the atmosphere. The hot shell of the waveguide has a different index of refraction (n) from that of the surrounding air layers and as such serves to internally reflect portions of the entering solar rays entering an aperture in the hot shell, toward the tip of the cone and a solar energy storage component positioned there, thus providing a virtual solar energy concentration system. In another embodiment, the solar energy storage component shuts down or otherwise rejects incoming solar energy when fully charged, to mitigate damage to system components. | 07-02-2009 |
20100203351 | HIGH STRENGTH COMPOSITE MATERIALS AND RELATED PROCESSES - Composite materials exhibiting very high strength properties and other characteristics are disclosed. The materials comprise one or more nanomaterials dispersed within one or more matrix materials. The nanomaterials can be in a variety of forms, such as for example, carbon nanotubes and/or nanofibers. The matrix material can be glass, fused silicas, or metal. Also disclosed are various processes and operations to readily disperse and uniformly align the nanotubes and/or nanofibers in the flowing matrix material, during production of the composite materials. | 08-12-2010 |
20120152480 | NANO-ENGINEERED ULTRA-CONDUCTIVE NANOCOMPOSITE COPPER WIRE - Nano-composite structures are formed by pre-loading carbon nanotubes (CNTs) into at least one of a plurality of channels running the length of a cartridge, placing the pre-loaded cartridge in a piston chamber of a die-casting machine, creating a vacuum therein, and filing the piston chamber with molten metal to soak the pre-loaded cartridge and fill empty cartridge channels. Pressure is applied via the piston to eject the carbon nanotubes and molten metal from the cartridge channels and inject the nano-composite mixture into a rod-shaped die cavity. The internal diameter of the cavity is equal to or less than the final diameter of the nozzle. The nano-composite mixture is cooled to form a solid nano-composite rod having the first predetermined diameter, wherein the carbon nanotubes are aligned in a non-random manner. Furthermore, drawing down the nano-composite rod to smaller diameter wire further disperses the nanotubes along the length of the wire. | 06-21-2012 |