Patent application number | Description | Published |
20080230877 | SEMICONDUCTOR PACKAGE HAVING WIRE REDISTRIBUTION LAYER AND METHOD OF FABRICATING THE SAME - A semiconductor package and a method of fabricating the same. The method includes providing a semiconductor substrate on which a chip pad is formed. A wire redistribution layer connected to the chip pad is formed. An insulating layer which includes an opening exposing a portion of the wire redistribution layer is formed. A metal ink is applied within the opening to thereby form a bonding pad. The applied metal ink within the opening and the insulating layer can be cured simultaneously. | 09-25-2008 |
20090127717 | Semiconductor module - A semiconductor module may include a circuit substrate with a first die on the circuit substrate and a second die on the first die. The first die may include at least one first data input/output pad on a first peripheral portion of the first die and at least one first control/address pad on a third peripheral portion, the third peripheral portion being separate from the first peripheral portion of the first die. The second die may include at least one second data input/output pad on a second peripheral portion and at least one second control/address pad on a fourth peripheral portion. The second peripheral portion of the second die is not overlapped with the first peripheral portion of the first die in plan view. The fourth peripheral portion of the second die overlaps at least a portion of the third peripheral portion of the first die. | 05-21-2009 |
20090186446 | Semiconductor device packages and methods of fabricating the same - Provided are semiconductor device packages and methods for fabricating the same. In some embodiments, the method includes providing a semiconductor chip on a substrate with through electrodes formed in the substrate, and providing a capping layer on the substrate to receive the semiconductor chip in a recess formed in the capping layer. The capping layer is coupled to the substrate by a bonding layer formed on the substrate, and the capping layer covers the semiconductor chip provided on the substrate. The processing of the substrate and the capping layer can be separately performed, thus allowing the material for the capping layer and/or the substrate to be selected to reduce (e.g., to minimize) a difference between the thermal expansion coefficients of the capping layer material and the substrate material. | 07-23-2009 |
20090239336 | Semiconductor packages and methods of fabricating the same - A semiconductor package and module, and methods of fabricating the same are provided. A method of fabricating a semiconductor package may include bonding rear surfaces of first and second semiconductor chips to each other, each of the semiconductor chips having chip pads exposed on front surfaces. The method may also include forming an encapsulation portion configured to encapsulate side surfaces of the bonded semiconductor chips, forming via plugs configured to pass through the encapsulation portion, forming an insulating layer configured to expose surfaces of the chip pads and the via plugs on the exposed surfaces of the two semiconductor chips and surfaces of the encapsulation portion, and forming package pads on the exposed surfaces of the chip pads and the surfaces of the via plugs. | 09-24-2009 |
20090278561 | PROBE CARD HAVING REDISTRIBUTED WIRING PROBE NEEDLE STRUCTURE AND PROBE CARD MODULE USING THE SAME - The probe card is comprised of a probe card wafer, a plurality of through via electrodes penetrating the probe card wafer; and a plurality of redistributed wiring probe needle structures, each being connected to the through via electrodes protruding from a surface of the probe card wafer. | 11-12-2009 |
20090298234 | METHOD OF FABRICATING SEMICONDUCTOR CHIP PACKAGE, SEMICONDUCTOR WAFER, AND METHOD OF SAWING THE SEMICONDUCTOR WAFER - A method of fabricating a semiconductor chip package, in which a protection layer is formed on a scribe lane of a wafer including a plurality of semiconductor chips, an encapsulation layer is formed on the semiconductor chips and the protection layer, and at least two types of lasers having different respective wavelengths are sequentially irradiated to the scribe lane so as to separate the semiconductor chips. Therefore, the wafer can be protected from the laser that is used to saw the encapsulation layer. | 12-03-2009 |
20100022051 | Method of fabricating electronic device having stacked chips - A method of fabricating an electronic device having stacked chips is provided. The method includes forming a plurality of chips arranged in a row direction and at least one chip arranged in a column direction. A molding layer is formed between the chips. Grooves are formed in the molding layer between the chips arranged in the row direction. Conductive interconnections are formed on the substrate having the grooves. The substrate is sawn along an odd- or even-numbered one of the grooves to be separated into a plurality of unit substrates. At least one of the separated unit substrates is folded along an unsawn groove of the grooves. | 01-28-2010 |
20100244233 | Chip stack package and method of fabricating the same - Provided is a chip stack package and a method of manufacturing the same. A chip stack package may include a base chip including a base substrate, a base through via electrode penetrating the base substrate, a base chip pad connected to the base through via electrode, and a base encapsulant. The chip stack package may further include at least one stack chip on a surface of the base substrate. The chip stack package may also include an external connection terminal connected to the base through via electrode and the base chip pad and protruding from the base encapsulant, and an external encapsulant surrounding and protecting outer surfaces of the base chip and the at least one stack chip, wherein the chip through via electrode and the chip pad are connected to the base through via electrode and the base chip pad of the base chip. | 09-30-2010 |
20100285635 | CHIP STACK PACKAGE AND METHOD OF MANUFACTURING THE CHIP STACK PACKAGE - A chip stack package includes a substrate, a plurality of chips, a plurality of adhesive layers and a plug. The substrate has a wiring pattern and a seed layer formed on the wiring pattern. Each of the chips has an electrode pad and a first through-hole that penetrates the electrode pad. The chips are stacked such that the first through-holes are aligned on the seed layer of the substrate. The adhesive layers are interposed between the substrate and one of the chips, as well as between the chips. Each of the adhesive layers has a second through-hole connected to the first through-hole. The plug fills up the first through-holes and the second through-holes and electrically connects the electrode pads to the wiring pattern of the substrate. A cross-sectional area of the plug in the second through-holes may be larger than that of the plug in the first through-holes. | 11-11-2010 |
20110097891 | Method of Manufacturing the Semiconductor Device - A method of manufacturing semiconductor device includes preparing a substrate having a first surface and a second surface opposite to the first surface. A first insulation layer is formed on the second surface. A sacrificial layer is formed on the first insulation layer. An opening is formed to penetrate through the substrate and extend from the first surface to a portion of the sacrificial layer. A second insulation layer is formed on an inner wall of the opening. A plug is formed to fill the opening. The sacrificial layer is removed to expose a lower portion of the plug through the second surface. | 04-28-2011 |
20110104888 | SEMICONDUCTOR DEVICES HAVING REDISTRIBUTION STRUCTURES AND PACKAGES, AND METHODS OF FORMING THE SAME - Semiconductor devices and methods of forming the same, including forming a chip pad on a chip substrate, forming a passivation layer on the chip pad and the chip substrate, forming a first insulation layer on the passivation layer, forming a recess and a first opening in the first insulation layer, forming a second opening in the passivation layer to correspond to the first opening, forming a redistribution line in a redistribution line area of the recess, the first opening, and the second opening, forming a second insulation layer on the redistribution line and the first insulation layer, and forming an opening in the second insulation to expose a portion of the redistribution line as a redistribution pad. | 05-05-2011 |
20110115078 | FLIP CHIP PACKAGE - A flip chip package may include a semiconductor chip, a package substrate, a conductive magnetic bump and an anisotropic conductive member. The semiconductor chip may have a first pad. The package substrate may have a second pad confronting the first pad. The conductive magnetic bump may be interposed between the semiconductor chip and the package substrate to generate a magnetic force. The anisotropic conductive member may be arranged between the semiconductor chip and the package substrate. The anisotropic conductive member may have conductive magnetic particles induced toward the conductive magnetic bump by the magnetic force to electrically connect the first pad with the second pad. A predetermined number of the conductive magnetic particles may be positioned between the conductive magnetic bump and the pad, so that an electrical connection reliability between the pads may be increased. | 05-19-2011 |
20110272819 | WAFER LEVEL PACKAGE AND METHODS OF FABRICATING THE SAME - In one embodiment, a wafer level package includes a rerouting pattern formed on a semiconductor substrate and a first encapsulant pattern overlying the rerouting pattern. The first encapsulant pattern has a via hole to expose a portion of the rerouting pattern. The package additionally includes an external connection terminal formed on the exposed portion of the rerouting pattern. An upper section of the sidewall and a sidewall of the external connection terminal may be separated by a gap distance. The gap distance may increase toward an upper surface of the encapsulant pattern. | 11-10-2011 |
20110292708 | 3D SEMICONDUCTOR DEVICE - A three-dimensional (3D) semiconductor device may include a stack of chips, including a master chip and one or more slave chips. I/O connections of slave chips need not be connected to channels on a motherboard, and only electrode pads of a master chip may be connected to the channels. Only the master chip may provide a load to the channels. A through-substrate via (TSV) boundary may be set on a data input path, a data output path, an address/command path, and/or a clock path of a semiconductor device in which the same type of semiconductor chips are stacked. | 12-01-2011 |
20120104631 | SEMICONDUCTOR MODULE - A semiconductor module may include a circuit substrate with a first die on the circuit substrate and a second die on the first die. The first die may include at least one first data input/output pad on a first peripheral portion of the first die and at least one first control/address pad on a third peripheral portion, the third peripheral portion being separate from the first peripheral portion of the first die. The second die may include at least one second data input/output pad on a second peripheral portion and at least one second control/address pad on a fourth peripheral portion. The second peripheral portion of the second die is not overlapped with the first peripheral portion of the first die in plan view. The fourth peripheral portion of the second die overlaps at least a portion of the third peripheral portion of the first die. | 05-03-2012 |
20140233292 | 3D SEMICONDUCTOR DEVICE - A three-dimensional (3D) semiconductor device may include a stack of chips, including a master chip and one or more slave chips. I/O connections of slave chips need not be connected to channels on a motherboard, and only electrode pads of a master chip may be connected to the channels. Only the master chip may provide a load to the channels. A through-substrate via (TSV) boundary may be set on a data input path, a data output path, an address/command path, and/or a clock path of a semiconductor device in which the same type of semiconductor chips are stacked. | 08-21-2014 |