Patent application number | Description | Published |
20100327250 | PHASE CHANGE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A phase change memory device having a strain transistor and a method of making the same are presented. The phase change memory device includes a semiconductor substrate, a junction word line, switching diodes, and a strain transistor. The semiconductor substrate includes a cell area and a core/peri area. The junction word line is formed in the cell area of the semiconductor substrate and includes a strain stress supplying layer doped with impurities. The switching diodes are electrically coupled to the junction word line. The strain transistor is formed in the core/peri area of the substrate and acts as a driving transistor. | 12-30-2010 |
20110266516 | PHASE CHANGE MEMORY DEVICE CAPABLE OF REDUCING DISTURBANCE AND METHOD OF MANUFACTURING THE SAME - A phase change memory device includes a plurality of word lines, a plurality of bit lines disposed to be crossed with the plurality of word lines, switching devices disposed at intersections of the plurality of word lines and the plurality of bit lines, heating electrodes connected to the switching devices respectively, heat absorbing layers disposed between adjacent heating electrodes, and phase change layers formed on the heating electrodes and the heat absorbing layers and extended in the same direction of the bit line. | 11-03-2011 |
20120156840 | PHASE CHANGE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A phase change memory device having a strain transistor and a method of making the same are presented. The phase change memory device includes a semiconductor substrate, a junction word line, switching diodes, and a strain transistor. The semiconductor substrate includes a cell area and a core/peri area. The junction word line is formed in the cell area of the semiconductor substrate and includes a strain stress supplying layer doped with impurities. The switching diodes are electrically coupled to the junction word line. The strain transistor is formed in the core/peri area of the substrate and acts as a driving transistor. | 06-21-2012 |
20130334488 | VERTICAL MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A vertical memory device capable of minimizing a cell size and improving current drivability and a method of fabricating the same are provided. The vertical memory device includes a common source region and source regions formed on the common source region and extending in a first direction. Channel regions are formed on each of the source regions, the channel regions extending in the first direction. Trenches are formed between the channel regions. A drain region is formed on each of the channel regions. A conductive layer is formed its on a side of each of the channel regions, the conductive layer extending to the first direction. A data storage material is formed on each of the drain regions. | 12-19-2013 |
20140054538 | 3-DIMENSIONAL STACK MEMORY DEVICE - A 3-dimensional stack memory device includes a semiconductor substrate, a stacked active pattern configured so that a plurality of stripe shape active regions and insulation layers are stacked alternatively over the semiconductor substrate, a gate electrode formed in the stacked active pattern, a source and drain formed at both sides of the gate electrode in each of the plurality of active regions, a bit line formed on one side of the drain to be connected to the drain, a resistive device layer formed on one side of the source to be connected to the source, and a source line connected to the resistive device layer. The source is configured of an impurity region having a first conductivity type, and the drain is configured of an impurity region having a second conductivity type different from the first conductivity type. | 02-27-2014 |
20140113427 | PHASE-CHANGE RANDOM ACCESS MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A phase-change random access memory (PCRAM) device includes a semiconductor substrate; switching elements formed on the semiconductor substrate; a plurality of phase-change structures formed on the switching elements; and heat absorption layers buried between the plurality of phase-change structures, wherein the plurality of phase-change structures are insulated from the heat absorption layers. | 04-24-2014 |
20140117304 | VARIABLE RESISTANCE MEMORY DEVICE - A variable resistance memory device includes a plurality of column selection switches, a plurality of variable resistance memory cells configured to be stacked and selected by the plurality of column selection switches, and a bit line connected to the plurality of variable resistance memory cells. Each of the plurality of variable resistance memory cells includes an ovonic threshold switch (OTS) element selectively driven by a plurality of word lines arranged to be stacked and a variable resistor connected in parallel to the OTS element. | 05-01-2014 |
20140160839 | SEMICONDUCTOR INTERGRATED CIRCUIT DEVICE, METHOD OF MANUFACTURING THE SAME, AND METHOD OF DRIVING THE SAME - A semiconductor integrated circuit device, a method of manufacturing the same, and a method of driving the same are provided. The device includes a semiconductor substrate, an upper electrode extending from a surface of the semiconductor substrate; a plurality of switching structures extending from both sidewalls of the upper electrode in a direction parallel to the surface of the semiconductor substrate, and a phase-change material layer disposed between the plurality of switching structures and the upper electrode. | 06-12-2014 |
20140162429 | SEMICONDUCTOR INTERGRATED CIRCUIT DEVICE, METHOD OF MANUFACTURING THE SAME, AND METHOD OF DRIVING THE SAME - A semiconductor integrated circuit device, a method of manufacturing the same, and a method of driving the same are provided. The device includes a semiconductor substrate, an upper electrode extending from a surface of the semiconductor substrate; a plurality of switching structures extending from both sidewalls of the upper electrode in a direction parallel to the surface of the semiconductor substrate, and a phase-change material layer disposed between the plurality of switching structures and the upper electrode. | 06-12-2014 |
20140166971 | VARIABLE RESISTANCE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A variable resistance memory device includes a semiconductor substrate having a vertical transistor with a shunt gate that increases an area of a gate of the vertical transistor. | 06-19-2014 |
20140167030 | VERTICAL TYPE SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A vertical memory device and a method of fabricating the same are provided. The vertical type semiconductor device includes a common source region formed in a cell area of a semiconductor substrate. A channel region is formed on the common source region. The channel region has a predetermined height and a first diameter. A drain region is formed on the channel region. The drain region has a predetermined height and a second diameter larger than the first diameter. A first gate electrode surrounding the channel region. | 06-19-2014 |
20140239247 | TRANSISTOR, RESISTANCE VARIABLE MEMORY DEVICE INCLUDING THE SAME, AND MANUFACTURING METHOD THEREOF - A resistance variable memory device including a vertical transistor includes an active pillar including a channel region, a source formed in one end of the channel region, and a lightly doped drain (LDD) region and a drain formed in the other end of the channel region, a first gate electrode formed to surround a periphery of the LDD region and having a first work function, and a second gate electrode formed to be connected to the first gate electrode and to surround the channel region and having a second work function that is higher than the first to work function. | 08-28-2014 |
20140248750 | VERTICAL TYPE SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A vertical memory device and a method of fabricating the same are provided. The vertical type semiconductor device includes a common source region formed in a cell area of a semiconductor substrate. A channel region is formed on the common source region. The channel region has a predetermined height and a first diameter. A drain region is formed on the channel region. The drain region has a predetermined height and a second diameter larger than the first diameter. A first gate electrode surrounding the channel region. | 09-04-2014 |
20140268996 | VARIABLE RESISTANCE MEMORY DEVICE AND METHOD OF DRIVING THE SAME - A variable resistance memory device and a driving method thereof are provided. The variable resistance memory device includes a base layer and a pillar-shaped gate electrode formed on the base layer and extending substantially perpendicular to a surface of the base layer. A current transfer layer is formed to surround the pillar-shaped gate electrode. A variable resistance layer formed in an outer portion of the current transfer layer. A blocking layer blocks a path of current flowing through the current transfer layer based on a voltage applied voltage to the pillar-shaped gate electrode, and diverts the current flowing through the current transfer layer to the variable resistance layer. | 09-18-2014 |
20140299831 | 3D VARIABLE RESISTANCE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A 3D variable resistance memory device and a method of manufacturing the same are provided. A semiconductor substrate includes a peripheral area, having a top surface, wherein a peripheral circuit is formed in the peripheral area. The peripheral circuit includes a driving transistor formed on a surface of the semiconductor substrate, wherein the semiconductor substrate forms the channel of the driving transistor. The semiconductor substrate includes a cell area, having a top surface, wherein a height of the top surface of the cell area is lower than a height of the top surface of the peripheral area, thereby defining a trench in the cell area. A plurality of memory cells, each include a switching transistor formed on the semiconductor substrate in the cell area, a channel extending in a direction substantially perpendicular to a surface of the semiconductor substrate, and a variable resistance layer that selectively stores data in response to the switching transistor. | 10-09-2014 |
20140301128 | 3D VARIABLE RESISTANCE MEMORY DEVICE HAVING JUNCTION FET AND DRIVING METHOD THEREOF - A 3D variable resistance memory device having a junction FET and a driving method thereof are provided. The variable resistance memory device includes a semiconductor substrate and a string selection switch formed on the semiconductor substrate. A channel layer is formed on the column string selection switch. A plurality of gates stacked along a length of the channel layer and each of the gates contacts an outer side of the channel layer. A variable resistance layer is formed on an inner side of the channel layer, and contacts the channel layer. | 10-09-2014 |
20140321193 | 3D VARIABLE RESISTANCE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A variable resistance memory device includes a plurality of cell gate electrodes extending in a first direction, wherein the plurality of cell gate electrodes are stacked in a second direction that is substantially perpendicular to the first direction. A gate insulating layer surrounds each cell gate electrode of the plurality of cell gate electrodes and a cell drain region is formed on two sides of the each cell gate electrode of the plurality of cell gate electrodes. A channel layer extends in the second direction along the stack of the plurality of cell gate electrodes, and a variable resistance layer contacting the channel layer. | 10-30-2014 |
20150048292 | SEMICONDUCTOR DEVICE HAVING VERTICAL CHANNEL, RESISTIVE MEMORY DEVICE INCLUDING THE SAME, AND METHOD OF MANUFACTURING THE SAME - A semiconductor device, a resistive memory device including the same, and a method of manufacturing the same are provided. The semiconductor device includes a pillar extending substantially perpendicular from a semiconductor substrate, the pillar including an inner portion and an outer portion surrounding the inner portion. A junction region is formed in an upper region and a lower region of the vertical pillar, and a gate surrounds the pillar. The inner portion of the pillar includes a semiconductor layer having a lattice constant that is larger than a lattice constant of the outer portion of the pillar. | 02-19-2015 |
20150048293 | THREE-DIMENSIONAL SEMICONDUCTOR DEVICE, VARIABLE RESISTIVE MEMORY DEVICE INCLUDING THE SAME, AND METHOD OF MANUFACTURING THE SAME - A three-dimensional semiconductor device, a resistive variable memory device including the same, and a method of manufacturing the same are provided. The 3D semiconductor device includes a source formed of a first semiconductor material, a channel layer formed on the source and formed of the first semiconductor material, a lightly doped drain (LDD) region formed on the channel layer and formed of a second semiconductor material having a higher oxidation rate than that of the first semiconductor material, a drain formed on the LDD region and formed of the first semiconductor material, and a gate insulating layer formed on outer circumferences of the channel layer, the LDD region, and the drain. | 02-19-2015 |
20150048294 | VARIABLE RESISTIVE MEMORY DEVICE INCLUDING VERTICAL CHANNEL PMOS TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - A semiconductor device having a vertical channel, a variable resistive memory device including the same, and a method of manufacturing the same are provided. The semiconductor device having a vertical channel includes a vertical pillar formed on a semiconductor substrate and including an inner portion and an outer portion surrounding the inner portion, junction regions formed in the outer portion of the vertical pillar, and a gate formed to surround the vertical pillar. The inner portion of the vertical pillar has a lattice constant smaller than that of the outer portion of the vertical pillar. | 02-19-2015 |
20150048295 | SEMICONDUCTOR DEVICE HAVING FIN GATE, RESISTIVE MEMORY DEVICE INCLUDING THE SAME, AND METHOD OF MANUFACTURING THE SAME - A semiconductor device having a fin gate that improves an operation current, and a method of manufacturing the same are provided. The semiconductor device includes an active pillar formed on a semiconductor substrate, and including a first region and a second region surrounding at least one surface of the first region, and a fin gate extending to overlap an upper surface and a lateral surface of the active pillar. The first region of the active pillar is formed of a semiconductor layer having a lattice constant smaller than that of the second region of the active pillar. | 02-19-2015 |
20150048296 | SEMICONDUCTOR DEVICE HAVING FIN GATE, RESISTIVE MEMORY DEVICE INCLUDING THE SAME, AND METHOD OF MANUFACTURING THE SAME - A semiconductor device having a fin gate that improves an operation current, and a method of manufacturing the same. The semiconductor device includes an active pillar formed on a semiconductor substrate, the active pillar including an inner region and an outer region surrounding the inner region, and a fin gate overlapping an upper surface and a lateral surface of the active pillar. The inner portion of the active pillar includes a first semiconductor layer having a first lattice constant, and the outer region of the active pillar includes a second semiconductor layer having a second lattice constant smaller than the first lattice constant. | 02-19-2015 |
Patent application number | Description | Published |
20090020741 | PHASE CHANGE MEMORY DEVICE WITH REINFORCED ADHESION FORCE - A phase change memory device includes a semiconductor substrate having a plurality of phase change cell regions. A bottom electrode is formed in each phase change cell region of the semiconductor substrate. An insulation layer is formed on the semiconductor substrate to cover the bottom electrode, and the insulation layer includes a contact hole exposing the bottom electrode. A contact plug is formed within the contact hole. A stacked pattern comprising a phase change layer and a top electrode is formed over the insulation layer. In the phase change memory device a buffer layer is interposed between the insulation layer and the phase change layer to reinforce the adhesion force between them. The buffer layer prevents the phase change material from peeling off due to an inconstant adhesion force between the phase change material and the insulation layer. | 01-22-2009 |
20100065804 | PHASE CHANGE MEMORY DEVICE HAVING MULTIPLE METAL SILICIDE LAYERS AND METHOD OF MANUFACTURING THE SAME - A phase change memory device having multiple metal silicide layers which enhances the current driving capability of switching elements and a method of manufacturing the same are presented. The device also includes switching elements, heaters, stack patterns, top electrodes, bit lines, word line contacts and word lines. The bottom of the switching elements are in electrical contact with the lower metal silicide layer and with an active area of silicon substrate. An upper metal silicide layer is interfaced between the top of the switching elements and the heaters. The stack patterns include phase change layers and top electrodes and are between the heaters and the top electrodes are in electrical contact with the top electrodes. The bit lines contact with the top electrode contacts. The word line contacts to the lower metal silicide film. | 03-18-2010 |
20100065805 | PHASE CHANGE MEMORY DEVICE HAVING A BOTTLENECK CONSTRICTION AND METHOD OF MANUFACTURING THE SAME - A phase change memory device having a bottleneck constriction and method of making same are presented. The phase change memory device includes a semiconductor substrate, a lower electrode, an interlayer film, an insulator, a phase change layer and an upper electrode. The interlayer film is formed on the semiconductor substrate having the lower electrode. The interlayer film includes a laminate of a first insulating film, a silicon film and a second insulating film with a hole formed therethrough. The insulator is disposed along the exposed surface of the silicon film around the inner circumference of the hole. The phase change layer is embedded within the hole having the insulator which constricts the shape of the phase change layer to a bottleneck constriction. A method of manufacturing the phase change memory device is also provided. | 03-18-2010 |
20100108974 | PHASE CHANGE MEMORY DEVICE HAVING A DIODE THAT HAS AN ENLARGED PN INTERFACIAL JUNCTION AND METHOD FOR MANUFACTURING THE SAME - A phase change memory device that has a diode with an enlarged, i.e., bulging, PN interfacial junction and a corresponding fabrication method are presented. The phase change memory device includes a semiconductor substrate, an insulation layer, a diode, and a phase change memory cell. The insulation layer is placed on the semiconductor substrate and has a contact hole which is wider in a middle portion than the lower and upper portions of the contact hole. The diode is formed within the contact hole and PN interfacial junction at the wider middle portion of the diode within the contact hole. The phase change memory cell is formed on top of the diode. | 05-06-2010 |
20130223124 | VARIABLE RESISTIVE MEMORY DEVICE AND METHOD OF FABRICATING AND DRIVING THE SAME - Provided are a variable resistive memory device, and methods of fabricating and driving the same. The variable resistive memory device includes a plurality of memory cells arranged in a first direction and in a second direction different from the first direction, each of the plurality of memory cells comprising a variable resistor and a selection device serially connected to the variable resistor. A common wiring is electrically connected to first ends of the plurality of memory cells to apply a common reference voltage. Each wiring line of a plurality of wiring lines is electrically connected to second ends of the plurality of memory cells arranged n the plurality of rows oriented in the first direction. A plurality of selection lines are respectively connected to the selection devices of the plurality of memory cells to select any one of the plurality of memory cells via the plurality of wiring lines. | 08-29-2013 |
Patent application number | Description | Published |
20130134371 | PHASE-CHANGE RANDOM ACCESS MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A phase-change random access memory (PCRAM) device includes a semiconductor substrate; switching elements formed on the semiconductor substrate; a plurality of phase-change structures formed on the switching elements; and heat absorption layers buried between the plurality of phase-change structures, wherein the plurality of phase-change structures are insulated from the heat absorption layers. | 05-30-2013 |
20130153847 | RESISTIVE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A resistive memory device capable of improving an integration density is provided. The resistive memory device includes a semiconductor substrate, a plurality of resistive memory cells configured to be stacked on the semiconductor substrate and insulated from one another, where each of the plurality of resistive memory cells includes a switching transistor and a resistive device layer electrically connected to the switching transistor, a common source line electrically connected to the plurality of stacked resistive memory cells, and a bit line electrically connected to the plurality of stacked resistive memory cells and being insulated from the common source line. | 06-20-2013 |
20130153848 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor memory device comprising a bit line extending in a first direction, a vertical gate cell including a gate oxide layer and a gate metal layer that are formed in a pillar shape, a lower electrode and a data storage material layer formed on the vertical gate cell, and an interconnection layer formed on the data storage material layer. | 06-20-2013 |
20130153851 | STACK TYPE SEMICONDUCTOR MEMORY DEVICE - A stack type memory device includes a semiconductor substrate; a plurality of bit lines arranged and stacked on the semiconductor substrate; a plurality of word lines formed on the plurality of bit lines; a plurality of interconnection units, each extending from a respective word line toward a respective one of the plurality of bit lines; and a plurality of memory cells connected between the plurality of bit lines and the interconnection units extending from the plurality of word lines, respectively. | 06-20-2013 |
20130258752 | STACK MEMORY APPARATUS - A stack memory apparatus is provided. The stack memory apparatus includes a semiconductor substrate, and a plurality of memory cells, each including a switching element and a variable resister connected in parallel, stacked on the semiconductor substrate. The plurality of memory cells is configured to be connected to each other in series. | 10-03-2013 |
20130313502 | HIGH DENSITY VARIABLE RESISTIVE MEMORY AND METHOD OF FABRICATING THE SAME - A high density variable resistive random access memory device and a method of fabricating the same are provided. The device includes first word lines, each separated from each other by a width of first word line; bit lines, each separated from each other by a width of bit line; and second word lines, each located between two adjacent first word lines, wherein the widths of first word line and the bit line are substantially same, and the bit lines are located over the first and second word lines. | 11-28-2013 |
20130313504 | RESISTIVE MEMORY DEVICE AND FABRICATION METHOD THEREOF - A resistive memory device capable of suppressing disturbance between cells and a fabrication method thereof are provided. The resistive memory device includes a word line formed, in a first direction, on a semiconductor substrate, lower access structures, each having a pillar shape, formed on the word line, a first insulating layer formed around an outer circumference of each of the lower access structures, a heat-absorption layer formed on a surface of each of the to heat-absorption layers, a variable resistive material formed on the lower access structures, and an upper electrode formed on each variable resistive material. | 11-28-2013 |