Patent application number | Description | Published |
20150214982 | BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 64800 AND CODE RATE OF 7/15 AND QUADRATURE PHASE SHIFT KEYING, AND BIT INTERLEAVING METHOD USING SAME - A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 7/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for quadrature phase shift keying (QPSK) modulation. | 07-30-2015 |
20150229328 | MODULATOR AND MODULATION METHOD USING NON-UNIFORM 16-SYMBOL SIGNAL CONSTELLATION FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING 2/15 CODE RATE - A modulator and a modulation method using a non-uniform 16-symbol signal constellation are disclosed. The modulator includes a memory and a processor. The memory receives a codeword corresponding to a low-density parity check (LDPC) code having a code rate of 2/15. The processor maps the codeword to 16 symbols of the non-uniform 16-symbol signal constellation on a 4-bit basis. | 08-13-2015 |
20150229334 | MODULATOR AND MODULATION METHOD USING NON-UNIFORM 16-SYMBOL SIGNAL CONSTELLATION FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING 7/15 CODE RATE - A modulator and a modulation method using a non-uniform 16-symbol signal constellation are disclosed. The modulator includes a memory and a processor. The memory receives a codeword corresponding to a low-density parity check (LDPC) code having a code rate of 7/15. The processor maps the codeword to 16 symbols of the non-uniform 16-symbol signal constellation on a 4-bit basis. | 08-13-2015 |
20150229335 | MODULATOR AND MODULATION METHOD USING NON-UNIFORM 16-SYMBOL SIGNAL CONSTELLATION FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING 3/15 CODE RATE - A modulator and a modulation method using a non-uniform 16-symbol signal constellation are disclosed. The modulator includes a memory and a processor. The memory receives a codeword corresponding to a low-density parity check (LDPC) code having a code rate of 3/15. The processor maps the codeword to 16 symbols of the non-uniform 16-symbol signal constellation on a 4-bit basis. | 08-13-2015 |
20150229336 | MODULATOR AND MODULATION METHOD USING NON-UNIFORM 16-SYMBOL SIGNAL CONSTELLATION FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING 4/15 CODE RATE - A modulator and a modulation method using a non-uniform 16-symbol signal constellation are disclosed. The modulator includes a memory and a processor. The memory receives a codeword corresponding to a low-density parity check (LDPC) code having a code rate of 4/15. The processor maps the codeword to 16 symbols of the non-uniform 16-symbol signal constellation on a 4-bit basis. | 08-13-2015 |
20150236720 | BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 64800 AND CODE RATE OF 5/15 AND 64-SYMBOL MAPPING, AND BIT INTERLEAVING METHOD USING SAME - A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 5/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping. | 08-20-2015 |
20150236722 | BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 64800 AND CODE RATE OF 3/15 AND 16-SYMBOL MAPPING, AND BIT INTERLEAVING METHOD USING SAME - A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 16-symbol mapping. | 08-20-2015 |
20150256202 | BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 64800 AND CODE RATE OF 4/15 AND 256-SYMBOL MAPPING, AND BIT INTERLEAVING METHOD USING SAME - A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256-symbol mapping. | 09-10-2015 |