Patent application number | Description | Published |
20100014339 | Semiconductor memory device and memory access method - A semiconductor memory device includes: first and second memory mats; first and second local input output lines coupled to the first memory mat via a first amplifier circuit; third and fourth local input output lines different from the first and second local input output lines, third and fourth local input output lines coupled to the second memory mat via a second amplifier circuit; a third amplifier circuit coupled between the first local input output line and a first main input output line; a fourth amplifier circuit coupled between the third local input output line and a second main input output line different from the first main input output line; and a first switch coupled between the second and third local input output lines and connecting the second local input output line to the fourth amplifier circuit when the first memory mat is activated and the second memory mat is not activated. | 01-21-2010 |
20100327459 | SEMICONDUCTOR DEVICE HAVING PLURALITY OF WIRING LAYERS AND DESIGNING METHOD THEREOF - A semiconductor device includes first and second wirings formed in a first wiring layer and extending parallel to an X direction, third and fourth wirings formed in a third wiring layer and extending parallel to a Y direction; fifth and sixth wirings formed in a second wiring layer positioned between the first and second wiring layers, a first contact conductor that connects the first wiring to the third wiring; and a second contact conductor that connects the second wiring to the fourth wiring. The first and second contact conductors are arranged in the X direction. According to the present invention, because the first and second contact conductors that connect wiring layers that are two or more layers apart are arranged in one direction, a prohibited area that is formed in the second wiring layer can be made narrower. Therefore, the flexibility of the layout of the second wiring layer is enhanced and the restriction on the wiring density can be relaxed. | 12-30-2010 |
20100327966 | SEMICONDUCTOR DEVICE HAVING CIRCUIT BLOCKS WITH MUTUALLY THE SAME CIRCUIT CONFIGURATION - To include a plurality of circuit blocks each including a plurality of nonvolatile memory elements arranged in the X direction, a plurality of comparing circuits that are respectively allocated to the nonvolatile memory elements, and a determining circuit that is commonly allocated to the comparing circuits. The nonvolatile memory elements included in a predetermined circuit block among the circuit blocks are arranged in a first area. The comparing circuits and the determining circuit included in the predetermined circuit block are arranged side by side in the X direction in a second area that is located in the Y direction with respect to the first area. With this arrangement, because the circuit block becomes a shaped block, even when a plurality of circuit blocks are repeatedly arranged, it is possible to realize a further reduction of the chip area. | 12-30-2010 |
20100328985 | SEMICONDUCTOR DEVICE HAVING PLURAL CIRCUIT BLOCKS LAID OUT IN A MATRIX FORM - To include an input circuit block to which a plurality of bits are input and a processing circuit block that processes an internal signal output from the input circuit block. The input circuit block includes a plurality of unit input circuits arranged in an X direction to which the bits are input, respectively. Each of the unit input circuits includes an input wiring pattern that extends in a Y direction and a transistor of which a control electrode is connected to a corresponding one of the input wiring pattern. Coordinates of the input wiring pattern and the transistor corresponding to the input wiring pattern in the X direction do not overlap with each other. With this arrangement, by sharing the input wiring pattern between circuit blocks adjacent to each other in the Y direction, it is possible to reduce the number of pre-decode wirings. | 12-30-2010 |
20110102955 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first pad, and a sub-trunk line elongated in a first direction; a main-trunk line arranged between the first pad and the sub-trunk line and elongated in the first direction. The semiconductor device further includes a first plug line elongated in a second direction crossing the first direction, the first plug line being connected between the first pad and the main-trunk line without being direct contact with the sub-trunk line. The semiconductor device further includes a second plug line elongated in the second direction, the second plug line being connected between the main-trunk line and the sub-trunk line, and a first element coupled to the sub-trunk line. | 05-05-2011 |
20110254617 | SEMICONDUCTOR DEVICE - A semiconductor device includes a reduced-power-consumption circuit block which includes first and second power lines, and a first circuit cell. The first circuit cell includes a first functional-element-free region. The first functional-element-free region includes a first driver circuit configured to connect and disconnect the first power line and the second power line. | 10-20-2011 |
20120039144 | Semiconductor device with shortened data read time - A semiconductor device includes: a plurality of memory cell arrays arranged along a predetermined direction; a plurality of bit lines to read data stored in a plurality of memory elements; a plurality of sense amplifier sections that amplify potentials appearing on selected bit lines, that amplify potentials in opposite phase to the potentials, and that output data signals and inverted data signals; a data output circuit that outputs the data to an external circuit based on the data signals and the inverted data signals; and a plurality of local signal lines extending parallel to the predetermined direction, to transmit the data signal and the inverted data signals to the data output circuit, wherein the local signal lines include two adjacent signal lines which are positionally switched around in a direction perpendicular to the predetermined direction alternately at predetermined intervals. | 02-16-2012 |
20120127773 | SEMICONDUCTOR DEVICE HAVING DATA BUS - A semiconductor device is disclosed which comprises a first wiring layer, a second wiring layer formed over the first wiring layer, data input/output terminals, and a data bus formed in the first and second wiring layers. The data bus includes N data lines transmitting data between a predetermined circuit and the input/output terminals. M first data lines among the N data lines have a length shorter than a predetermined length and residual N-M second data lines have a length longer than the predetermined length. Shield lines adjacent to the N data lines are formed in the first and second layers. The N data lines are arranged at positions at which the data lines do not overlap one another in a stacking direction of the first and second wiring layers. | 05-24-2012 |
20120236669 | SEMICONDUCTOR DEVICE HAVING COMPENSATION CAPACITANCE - Disclosed herein is a device that includes: first and second memory mats each including a plurality of bit lines; a sense area arranged between the first and second memory mats; a column selection line provided on the first memory mat; and a compensation capacitance provided on the second memory mat. The sense area includes a plurality of sense amplifiers. Each of the sense amplifiers is connected to an associated one or ones of the bit lines. At least one of the sense amplifiers is selected based on a column selection signal supplied via the column selection line. At least a part of the compensation capacitance is formed in a same wiring layer as the column selection line. | 09-20-2012 |
20120243341 | SEMICONDUCTOR DEVICE HAVING PLURAL DATA BUSES AND PLURAL BUFFER CIRCUITS CONNECTED TO DATA BUSES - Disclosed herein is a device that includes a plurality of buffer circuits and data buses coupled to the buffer circuits. Each of the data buses includes first and second portions. The first portions of the data buses are arranged at a first pitch in the second direction, and the second portions of the data buses are arranged at a second pitch in the second direction, the second pitch being smaller than the first pitch. | 09-27-2012 |
20120247812 | SEMICONDUCTOR DEVICE WITH POWER SUPPLY LINE SYSTEM OF REDUCED RESISTANCE - A semiconductor device with a power wiring system. The device includes a multi-level wiring structure including a lower-level wiring layer and an upper-level wiring layer over the lower-level wiring layer, and the power wiring system includes a first power supply line and a second power supply line provided as the first-level wiring layer and extending in a first direction in substantially parallel to each other, a third power supply line provided as the upper-level wiring layer and extending in the first direction with overlapping the first power supply line, the first and third power supply lines conveying first and second power voltages, respectively, which are different from each other, and a fourth power supply line provided as the upper-level wiring layer and extending in the first direction with overlapping the second power supply line, the second and fourth power supply lines conveying the second and first power voltages, respectively. | 10-04-2012 |
20120256243 | SEMICONDUCTOR DEVICE FOR REDUCING INTERCONNECT PITCH - A semiconductor device includes a plurality of transistors formed on a semiconductor substrate, a first local wiring which is electrically connected to at least one of the plurality of transistors and extending in a first direction, a second local wiring which is formed above the first local wiring and which electrically connects to at least one of the plurality of transistors and extends in a second direction, a plurality of first wirings which are formed above the second local wiring and which extend in a third direction, at least each of the plurality of first wirings being electrically connected to the first local wiring and the second local wiring, respectively, and a second wiring which is formed above the first wiring and which electrically connects to at least one of the plurality of first wirings and extends in a fourth direction. | 10-11-2012 |
20120267749 | SEMICONDUCTOR DEVICE HAVING FUSE ELEMENTS AND GUARD RING SURROUNDING THE FUSE ELEMENTS - The semiconductor memory device has a fuse area in which fuse elements for registering addresses of defective memory cells are arranged. A guard ring is formed around the fuse area and is covered by a passivation film. The passivation film above the fuse area has an opening. The guard ring has a first ring in a first layer, a second ring in a second layer and a third ring in a third layer. These rings are connected by a first connecting ring and a second connecting ring. The first ring is positioned at an inward part of the second ring to provide an area unoccupied by the first ring beneath the second ring. | 10-25-2012 |
20120314471 | SEMICONDUCTOR DEVICE - A semiconductor device comprises a first region and a second region. The first region includes a plurality of memory cells each of which holds respective data and a plurality of sense amplifiers that respectively amplify the data in the plurality of memory cells, based on a first voltage. The second region is provided along one side of the first region and includes a first power supply generation circuit that generates the first voltage, based on a second voltage. The second voltage being supplied to the first power supply circuit by a first power supply interconnect extends on the first region in a first direction parallel to the one side of the first region. | 12-13-2012 |
20120319228 | SEMICONDUCTOR DEVICE - A semiconductor device is disclosed, which includes first and second power supply pads supplied with first and second power voltages, respectively, a first protection circuit coupled between the first and second power supply pads, and an internal circuit including a first power line and a plurality of transistors electrically coupled to the first power line. The first power line includes first and second portions, and the first portion is electrically connected to the first power supply pad. The device further includes a second protection circuit coupled between the second portion of the first power line and the second power supply pad. | 12-20-2012 |
20130032925 | SEMICONDUCTOR DEVICE - A semiconductor device comprises a first external terminal having a first size, a plurality of second external terminals each having a second size smaller than the first size, an external terminal area in which the first external terminal and the second external terminals are arranged, and a plurality of wires connecting between the second external terminals and a plurality of circuits formed adjacent to the external terminal area and corresponding to the second external terminals. The second external terminals and the wires constitute a plurality of interfaces. Each of the interfaces includes at least one adjustment portion that adjusts a time constant of the wire so that the wires have the same time constant. At least part of the adjustment portions is located in a margin area produced in the external terminal area by a difference between the first size and the second size. | 02-07-2013 |
20130033916 | SEMICONDUCTOR DEVICE HAVING PLURAL CIRCUIT BLOCKS THAT OPERATE THE SAME TIMING - Disclosed herein is a device that includes first and second ports arranged in a first direction and first and second circuits arranged between the first and second ports. The first and second ports are coupled to the first and second circuits, respectively. The first and second circuits include first and second sub circuits that control an operation timing thereof based on a timing signal, respectively. The control signal is transmitted through a control line extending in a second direction. Distances between the control line and the first and second sub circuits in the first direction are the same as each other. A coordinate of the control line in the first direction is different from an intermediate coordinate between coordinates of the first and second ports in the first direction. | 02-07-2013 |
20130154025 | SEMICONDUCTOR DEVICE INCLUDING CAPACITOR STABILIZING VARIATION OF POWER SUPPLY VOLTAGE - Disclosed herein is a semiconductor device that includes a first line supplied with a first voltage, a second line supplied with a second voltage, a first node, at least one first capacitor connected between the first line and the first node, at least one second capacitor connected between the node and the second line, and a protective element connected between the first node and the second line in parallel to the second capacitor. | 06-20-2013 |
20130193586 | SEMICONDUCTOR DEVICE HAVING PLURALITY OF WIRING LAYERS AND DESIGNING METHOD THEREOF - A semiconductor device includes first and second wirings formed in a first wiring layer and extending parallel to an X direction, third and fourth wirings formed in a third wiring layer and extending parallel to a Y direction; fifth and sixth wirings formed in a second wiring layer positioned between the first and second wiring layers, a first contact conductor that connects the first wiring to the third wiring; and a second contact conductor that connects the second wiring to the fourth wiring. The first and second contact conductors are arranged in the X direction. Because the first and second contact conductors that connect wiring layers that are two or more layers apart are arranged in one direction, a prohibited area that is formed in the second wiring layer can be made narrower. | 08-01-2013 |
20130242683 | SEMICONDUCTOR DEVICE HAVING COMPENSATION CAPACITORS FOR STABILIZING OPERATION VOLTAGE - Disclosed herein is a device that includes first and second memory cell arrays each including a plurality of memory cells, a first power supply line supplying a first voltage to the first memory cell array, a second power supply line supplying the first voltage to the second memory cell array, and a first capacitive element. The first capacitive element is electrically connected to the first power supply line and is electrically disconnected from the second power supply line when the first memory cell array is activated and the second memory cell array is deactivated. The first capacitive element is electrically connected to the second power supply line and is electrically disconnected from the first power supply line when the second memory cell array is activated and the first memory cell array is deactivated. | 09-19-2013 |
20130258792 | SEMICONDUCTOR DEVICE HAVING COMPENSATION CAPACITOR TO STABILIZE POWER SUPPLY VOLTAGE - Disclosed herein is a device that includes: first and second memory cell arrays arranged in a first direction; a plurality of first bump electrodes disposed between the first and second memory cell arrays and arranged in line in a second direction crossing the first direction; a plurality of second bump electrodes disposed between the first bump electrodes and the second memory cell arrays and arranged in line in the second direction; a first area being between the first and second bump electrodes; a plurality of third bump electrodes disposed in the first area; and a first capacitor formed in the third area. | 10-03-2013 |
20130265840 | SEMICONDUCTOR DEVICE HAVING AUXILIARY POWER-SUPPLY WIRING - Disclosed herein is a semiconductor device that includes a signal wiring arranged on a first layer and extending over the circuit block or blocks in the first direction so as to reach the first circuit block and produce a free space above the first circuit block, the signal wiring being electrically connected to the first circuit block, a power-supply wiring arranged on a second layer and extending over the circuit block or blocks in the first direction so as to reach the first circuit block, the power-supply wiring supplying an operating voltage to the first circuit block and an auxiliary power-supply wiring being configured to enhance the operating voltage supplied by the power supply line, and the auxiliary power-supply wiring being formed in the free space produced by the arrangement of the signal wiring. | 10-10-2013 |
20130285258 | SEMICONDUCTOR DEVICE HAVING MESH-PATTERN WIRINGS - Disclosed herein is a device that includes: first lines formed on a first wiring layer extending in a first direction; second lines formed on a second wiring layer extending in a second direction; and conductor plugs connecting the first lines to the second lines such that the first and second lines form a mesh-structure wiring. The first lines include first enlarged portions at intersection positions where the first and second lines cross to each other, a width in the second direction of the first enlarged portions is wider than a line width of the first lines at other than the intersection position. The second lines include second enlarged portions at the intersection positions, a width in the first direction of the second enlarged portions is wider than a line width of the second lines at other than the intersection position. | 10-31-2013 |
20140112047 | SEMICONDUCTOR DEVICE HAVING DATA BUS - A semiconductor device is disclosed which comprises a first wiring layer, a second wiring layer formed over the first wiring layer, data input/output terminals, and a data bus formed in the first and second wiring layers. The data bus includes N data lines transmitting data between a predetermined circuit and the input/output terminals. M first data lines among the N data lines have a length shorter than a predetermined length and residual N-M second data lines have a length longer than the predetermined length. Shield lines adjacent to the N data lines are formed in the first and second layers. The N data lines are arranged at positions at which the data lines do not overlap one another in a stacking direction of the first and second wiring layers. | 04-24-2014 |
20140191416 | SEMICONDUCTOR DEVICE - A semiconductor device comprises a first external terminal having a first size, a plurality of second external terminals each having a second size smaller than the first size, an external terminal area in which the first external terminal and the second external terminals are arranged, and a plurality of wires connecting between the second external terminals and a plurality of circuits formed adjacent to the external terminal area and corresponding to the second external terminals. The second external terminals and the wires constitute a plurality of interfaces. Each of the interfaces includes at least one adjustment portion that adjusts a time constant of the wire so that the wires have the same time constant. At least part of the adjustment portions is located in a margin area produced in the external terminal area by a difference between the first size and the second size. | 07-10-2014 |
20150341001 | SEMICONDUCTOR DEVICE INCLUDING AMPLIFIER - Disclosed here is an apparatus that comprises an amplifier having first and second input nodes, first and second resistors, a first electrostatic discharge protection circuit coupled between the first input node and the first resistor, and a second electrostatic discharge protection circuit coupled between the second input node and the second resistor. | 11-26-2015 |
Patent application number | Description | Published |
20120068139 | MAGNETORESISTIVE ELEMENT AND MAGNETIC MEMORY - A magnetoresistive element according to an embodiment includes: a first ferromagnetic layer having an axis of easy magnetization in a direction perpendicular to a film plane; a second ferromagnetic layer having an axis of easy magnetization in a direction perpendicular to a film plane; a nonmagnetic layer placed between the first ferromagnetic layer and the second ferromagnetic layer; a first interfacial magnetic layer placed between the first ferromagnetic layer and the nonmagnetic layer; and a second interfacial magnetic layer placed between the second ferromagnetic layer and the nonmagnetic layer. The first interfacial magnetic layer includes a first interfacial magnetic film, a second interfacial magnetic film placed between the first interfacial magnetic film and the nonmagnetic layer and having a different composition from that of the first interfacial magnetic film, and a first nonmagnetic film placed between the first interfacial magnetic film and the second interfacial magnetic film. | 03-22-2012 |
20120068285 | MAGNETORESISTIVE EFFECT ELEMENT, MAGNETIC MEMORY, AND METHOD OF MANUFACTURING MAGNETORESISTIVE EFFECT ELEMENT - According to one embodiment, a magnetoresistive effect element includes a first magnetic layer including perpendicular anisotropy to a film surface and an invariable magnetization direction, the first magnetic layer having a magnetic film including an element selected from a first group including Tb, Gd, and Dy and an element selected from a second group including Co and Fe, a second magnetic layer including perpendicular magnetic anisotropy to the film surface and a variable magnetization direction, and a nonmagnetic layer between the first magnetic layer and the second magnetic layer. The magnetic film includes amorphous phases and crystals whose particle sizes are 0.5 nm or more. | 03-22-2012 |
20120069640 | MAGNETORESISTIVE ELEMENT AND MAGNETIC MEMORY - A magnetoresistive element according to an embodiment includes: a first and second magnetic layers having an easy axis of magnetization in a direction perpendicular to a film plane; and a first nonmagnetic layer interposed between the first and second magnetic layers, at least one of the first and second magnetic layers including a structure formed by stacking a first and second magnetic films, the second magnetic film being located closer to the first nonmagnetic layer, the second magnetic film including a structure formed by repeating stacking of a magnetic material layer and a nonmagnetic material layer at least twice, the nonmagnetic material layers of the second magnetic film containing at least one element selected from the group consisting of Ta, W, Hf, Zr, Nb, Mo, Ti, V, and Cr, one of the first and second magnetic layers having a magnetization direction that is changed by applying a current. | 03-22-2012 |
20120069642 | MAGNETORESISTIVE ELEMENT AND MAGNETIC RANDOM ACCESS MEMORY - According to one embodiment, a magnetoresistive element includes an electrode layer, a first magnetic layer, a second magnetic layer and a nonmagnetic layer. The electrode layer includes a metal layer including at least one of Mo, Nb, and W. The first magnetic layer is disposed on the metal layer to be in contact with the metal layer and has a magnetization easy axis in a direction perpendicular to a film plane and is variable in magnetization direction. The second magnetic layer is disposed on the first magnetic layer and has a magnetization easy axis in the direction perpendicular to the film plane and is invariable in magnetization direction. The nonmagnetic layer is provided between the first and second magnetic layers. The magnetization direction of the first magnetic layer is varied by a current that runs through the first magnetic layer, the nonmagnetic layer, and the second magnetic layer. | 03-22-2012 |
20120088125 | MAGNETORESISTIVE ELEMENT AND MAGNETIC MEMORY - A magnetoresistive element according to an embodiment includes: a base layer; a first magnetic layer formed on the base layer and having a changeable magnetization direction with an easy axis of magnetization in a direction perpendicular to a film plane; a first nonmagnetic layer formed on the first magnetic layer; and a second magnetic layer formed on the first nonmagnetic layer and having a fixed magnetization layer with an easy axis of magnetization in a direction perpendicular to the film plane. The first magnetic layer includes a ferrimagnetic layer having a DO | 04-12-2012 |
20130020659 | MAGNETORESISTIVE ELEMENT AND MAGNETIC MEMORY - A magnetoresistive element according to an embodiment includes: a first ferromagnetic layer having an axis of easy magnetization in a direction perpendicular to a film plane; a second ferromagnetic layer having an axis of easy magnetization in a direction perpendicular to a film plane; a nonmagnetic layer placed between the first ferromagnetic layer and the second ferromagnetic layer; a first interfacial magnetic layer placed between the first ferromagnetic layer and the nonmagnetic layer; and a second interfacial magnetic layer placed between the second ferromagnetic layer and the nonmagnetic layer. The first interfacial magnetic layer includes a first interfacial magnetic film, a second interfacial magnetic film placed between the first interfacial magnetic film and the nonmagnetic layer and having a different composition from that of the first interfacial magnetic film, and a first nonmagnetic film placed between the first interfacial magnetic film and the second interfacial magnetic film. | 01-24-2013 |
20140085971 | MAGNETORESISTIVE EFFECT ELEMENT - According to one embodiment, a magnetoresistive effect element includes the following structure. A first ferromagnetic layer has a variable magnetization direction. A second ferromagnetic layer has an invariable magnetization direction. A tunnel barrier layer is formed between the first and second ferromagnetic layers. An energy barrier between the first ferromagnetic layer and the tunnel barrier layer is higher than an energy barrier between the second ferromagnetic layer and the tunnel barrier layer. The second ferromagnetic layer contains a main component and an additive element. The main component contains at least one of Fe, Co, and Ni. The additive element contains at least one of Mg, Al, Ca, Sc, Ti, V, Mn, Zn, As, Sr, Y, Zr, Nb, Cd, In, Ba, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Hf, Ta, and W. | 03-27-2014 |
20140284592 | MAGNETORESISTIVE EFFECT ELEMENT AND MANUFACTURING METHOD THEREOF - According to one embodiment, a magnetoresistive effect element includes a first ferromagnetic layer, a tunnel barrier provided on the first ferromagnetic layer, and a second ferromagnetic layer provided on the tunnel barrier. The tunnel barrier includes a nonmagnetic mixture containing MgO and a metal oxide with a composition which forms, in a solid phase, a single phase with MgO. | 09-25-2014 |
20140284732 | MAGNETORESISTIVE EFFECT ELEMENT AND MANUFACTURING METHOD THEREOF - According to one embodiment, a magnetoresistive effect element includes a first ferromagnetic layer, a tunnel barrier formed on the first ferromagnetic layer, and a second ferromagnetic layer formed on the tunnel barrier layer. The tunnel barrier includes a nonmagnetic oxide having a spinel structure. Oxides forming the spinel structure are combined such that a single phase is formed by a solid phase in a component ratio region including a component ratio corresponding to the spinel structure and having a width of not less than 2%. | 09-25-2014 |
20150357557 | ELECTRONIC DEVICE - This technology provides an electronic device. An electronic device in accordance with an implementation of this document includes semiconductor memory, and the semiconductor memory includes a first magnetic layer having a variable magnetization direction; a second magnetic layer having a pinned magnetization direction; and a tunnel barrier layer interposed between the first magnetic layer and the second magnetic layer, wherein the second magnetic layer includes a ferromagnetic material with molybdenum (Mo) added thereto. | 12-10-2015 |
20160043300 | ELECTRONIC DEVICE - An electronic device includes semiconductor memory, the semiconductor memory including an under layer; a first magnetic layer located over the under layer and having a variable magnetization direction; a tunnel barrier layer located over the first magnetic layer; and a second magnetic layer located over the tunnel barrier layer and having a pinned magnetization direction, wherein the under layer includes a first metal nitride layer having a NaCl crystal structure and a second metal nitride layer containing a light metal. | 02-11-2016 |