Patent application number | Description | Published |
20150081572 | AUTOMATICALLY RECOMMENDING UPDATES BASED ON STORED LIFECYCLE INFORMATION - Lifecycle information indicative of a configuration and update state of a computer system are stored. Updates to the computer system are automatically recommended based on the lifecycle information. | 03-19-2015 |
20150082291 | UPDATE INSTALLER WITH TECHNICAL IMPACT ANALYSIS - An update installer generates an update display for a user that allows a user to select updates in an identified environment. The update installer accesses the objects and layers in the identified environment and displays an impact display identifying portions of the identified environment that will be affected by the selected updates, before the updates are installed. | 03-19-2015 |
20150082292 | AUTOMATICALLY RESOLVING CONFLICTS AFTER INSTALLATION OF SELECTED UPDATES IN A COMPUTER SYSTEM - An update installer generates an update display for a user that allows the user to select updates to be applied to a computer system. Conflicts that arise because of application of the updates to the computer system are automatically resolved and the results of the conflict resolution are displayed. | 03-19-2015 |
20150082293 | UPDATE INSTALLER WITH PROCESS IMPACT ANALYSIS - An update installer generates an update display for a user that displays available updates. The user can select updates, and the update installer accesses the business processes corresponding to the user's project and displays an impact analysis indicating the impact that the selected updates will have on the processes in the system. | 03-19-2015 |
20150082296 | AUTOMATIC INSTALLATION OF SELECTED UPDATES IN MULTIPLE ENVIRONMENTS - An update installer generates an update display for a user that allows the user to select updates be applied to a first environment. An export display allows the user to export the selected updates so they can be saved for installation in another environment. | 03-19-2015 |
20150317147 | DYNAMIC UPDATE INSTALLER FOR CUSTOMIZED SOFTWARE - A computer-implemented method of updating a system of customized software is provided. The method includes receiving an update request and collecting contextual information relative to the system of customized software. A query is generated for updates applicable to the system of customized software based on the contextual information. A query response is received indicative of at least one applicable update. A selection relative to the at least one applicable update is received. At least one update is selectively applied based on the selection. | 11-05-2015 |
20160048383 | ISV UPDATE DELIVERY - And update installer provides an ISV user interface display that allows an ISV to download manufacturer updates to a computer system. The update installer also allows the ISV to subsequently upload ISV updates that incorporate the manufacturer's updates and any additional ISV updates. The ISV update package is saved on a lifecycle system that can be accessed by a customer for installation of the ISV updates on the customer's system. | 02-18-2016 |
Patent application number | Description | Published |
20080307082 | Dynamically discovering a system topology - In one embodiment, the present invention includes a method for dynamically discovering a topology of a system having a plurality of point-to-point (PTP) links via a routine that communicates a link exchanged parameter with at least one component coupled to a system bootstrap processor (SBSP), sets a minimal set of routing infrastructure information based on the communication, and determines presence of a neighboring component to a target component based on a communication from the SBSP to the target component using the minimal set of routing infrastructure information. Other embodiments are described and claimed. | 12-11-2008 |
20090083528 | SYSTEM INFORMATION SYNCHRONIZATION IN A LINKS-BASED MULTI-PROCESSOR SYSTEM - Various embodiments described herein include one or more of systems, methods, firmware, and software to synchronize system information between processors during system boot in a links-based multi-processor system. Some embodiments synchronize data block by block through memory rather than piece by piece through registers by allowing a System Bootstrap Processor (“SBSP”) to directly access synchronization data in local memory of each of one or more Application Processors. These and other embodiments are described in greater detail below. | 03-26-2009 |
20090144476 | HOT PLUG IN A LINK BASED SYSTEM - Machine-readable medium, processes and systems for adding and/or removing components from a running computing device based upon a static topology table and a dynamic topology table are disclosed. | 06-04-2009 |
20090265472 | Method, System, and Apparatus for System Level Initialization - Multiple initialization techniques for system and component in a point-to-point architecture are discussed. Consequently, the techniques allow for flexible system/socket layer parameters to be tailored to the needs of the platform, such as, desktop, mobile, small server, large server, etc., as well as the component types such as IA32/IPF processors, memory controllers, IO Hubs, etc. Furthermore, the techniques facilitate powering up with the correct set of POC values, hence, it avoids multiple warm resets and improves boot time. In one embodiment, registers to hold new values, such as, Configuration Values Driven during Reset (CVDR), and Configuration Values Captured during Reset (CVCR) may be eliminated. | 10-22-2009 |
Patent application number | Description | Published |
20110154104 | Controlling Memory Redundancy In A System - In one embodiment, the present invention provides an ability to handle an error occurring during a memory migration operation in a high availability system. In addition, a method can be used to dynamically remap a memory page stored in a non-mirrored memory region of memory to a mirrored memory region. This dynamic remapping may be responsive to a determination that the memory page has been accessed more than a threshold number of times, indicating a criticality of information on the page. Other embodiments are described and claimed. | 06-23-2011 |
20110161592 | Dynamic system reconfiguration - In some embodiments system reconfiguration code and data to be used to perform a dynamic hardware reconfiguration of a system including a plurality of processor cores is cached and any direct or indirect memory accesses during the dynamic hardware reconfiguration are prevented. One of the processor cores executes the cached system reconfiguration code and data in order to dynamically reconfigure the hardware. Other embodiments are described and claimed. | 06-30-2011 |
20110179311 | INJECTING ERROR AND/OR MIGRATING MEMORY IN A COMPUTING SYSTEM - In some embodiments a request is received to perform an error injection or a memory migration, a mode is entered that blocks requests from agents other than a current processor core or thread, the error is injected or the memory is migrated, and the mode that blocks requests from the agents other than the current processor core or thread is exited. Other embodiments are described and claimed. | 07-21-2011 |
20130212426 | Controlling Memory Redundancy In A System - In one embodiment, the present invention provides an ability to handle an error occurring during a memory migration operation in a high availability system. In addition, a method can be used to dynamically remap a memory page stored in a non-mirrored memory region of memory to a mirrored memory region. This dynamic remapping may be responsive to a determination that the memory page has been accessed more than a threshold number of times, indicating a criticality of information on the page. Other embodiments are described and claimed. | 08-15-2013 |
20130290759 | ENHANCED SYSTEM SLEEP STATE SUPPORT IN SERVERS USING NON-VOLATILE RANDOM ACCESS MEMORY - A non-volatile random access memory (NVRAM) is used in a computer system to enhance support to sleep states. The computer system includes a processor, a non-volatile random access memory (NVRAM) that is byte-rewritable and byte-erasable, and power management (PM) module. A dynamic random access memory (DRAM) provides a portion of system address space. The PM module intercepts a request initiated by an operating system for entry into a sleep state, copies data from the DRAM to the NVRAM, maps the portion of the system address space from the DRAM to the NVRAM, and turns off the DRAM when transitioning into the sleep state. Upon occurrence of a wake event, the PM module returns control to the operating system such that the computer system resumes working state operations without the operating system knowing that the portion of the system address space has been mapped to the NVRAM. | 10-31-2013 |
20130304980 | AUTONOMOUS INITIALIZATION OF NON-VOLATILE RANDOM ACCESS MEMORY IN A COMPUTER SYSTEM - A non-volatile random access memory (NVRAM) is used in a computer system to store information that allows the NVRAM to autonomously initialize itself at power-on. The computer system includes a processor, an NVRAM controller coupled to the processor, and an NVRAM that comprises the NVRAM controller. The NVRAM is byte-rewritable and byte-erasable by the processor. The NVRAM stores a memory interface table containing information for the NVRAM controller to autonomously initialize the NVRAM upon power-on of the computer system without interacting with the processor and firmware outside of the NVRAM. The information is provided by the NVRAM controller to the processor to allow the processor to access the NVRAM. | 11-14-2013 |
20130339829 | Machine Check Summary Register - In some implementations, a processor may include a machine check architecture having a plurality of error reporting registers able to receive data for machine check errors. A summary register may include a plurality of settable locations that each represents at least one of the error reporting registers. One or more of the settable locations in the summary register may be set to indicate whether one or more of the error reporting registers maintain data for a machine check error. Accordingly, when a machine check error occurs, the summary register may be accessed to identify if any error reporting registers in a processor's view contain valid error data, rather than having to read each of the error reporting registers in the processor's view. | 12-19-2013 |
20140082262 | APPARATUS, METHOD AND SYSTEM THAT STORES BIOS IN NON-VOLATILE RANDOM ACCESS MEMORY - A non-volatile random access memory (NVRAM) is used in a computer system to perform multiple roles in the platform storage hierarchy. The NVRAM is byte-rewritable and byte-erasable by the processor. The NVRAM is coupled to the processor to be directly accessed by the processor without going through an I/O subsystem. The NVRAM stores a Basic Input and Output System (BIOS). During a Pre-Extensible Firmware Interface (PEI) phase of the boot process, the cache within the processor can be used in a write-back mode for execution of the BIOS. | 03-20-2014 |
20140143577 | POWER CONSERVATION BY WAY OF MEMORY CHANNEL SHUTDOWN - A method is described that includes deciding to enter a lower power state, and, shutting down a memory channel in a computer system in response where thereafter other memory channels in the computer system remain active so that computer remains operative while the memory channel is shutdown. | 05-22-2014 |
20140195876 | Memory Module Architecture - In accordance with some embodiments, memory modules containing phase change memory elements may be organized so that each memory integrated circuit includes both data and error correcting code. As a result of including the error correcting code in each integrated circuit, extra accesses of the memory module to extract the error correcting code can be avoided, improving the performance of the overall memory module in some embodiments. | 07-10-2014 |
20140297919 | APPARATUS AND METHOD FOR IMPLEMENTING A MULTI-LEVEL MEMORY HIERARCHY - A system and method are described for intelligently flushing data from a processor cache. For example, a system according to one embodiment of the invention comprises: a processor having a cache from which data is flushed, the data associated with a particular system address range; and a PCM memory controller for managing access to data stored in a PCM memory device corresponding to the particular system address range; the processor determining whether memory flush hints are enabled for the specified system address range, wherein if memory flush hints are enabled for the specified system address range then the processor sending a memory flush hint to a PCM memory controller of the PCM memory device and wherein the PCM memory controller uses the memory flush hint to determine whether to save the flushed data to the PCM memory device. | 10-02-2014 |
20150149735 | MEMORY SYSTEM - Provided is a device for use in a memory module coupled to a host memory controller over a bus, comprising memory module control logic to generate a request signal to a host memory controller having a pulse width greater than or equal to a minimum pulse width, wherein the minimum pulse width comprises a number of clock cycles needed to guarantee that the host memory controller detects the request signal, and wherein the pulse width of the request signal indicates at least one function in addition to the request signal to the host memory controller. | 05-28-2015 |
20150378615 | ACCELERATING BOOT TIME ZEROING OF MEMORY BASED ON NON-VOLATILE MEMORY (NVM) TECHNOLOGY - Methods and apparatus to accelerate boot time zeroing of memory based on Non-Volatile Memory (NVM) technology are described. In an embodiment, a storage device stores a boot version number corresponding to a portion of a non-volatile memory. A memory controller logic causes an update of the stored boot version number in response to each subsequent boot event. The memory controller logic returns a zero in response to a read operation directed at the portion of the non-volatile memory and a mismatch between the stored boot version number and a current boot version number. Other embodiments are also disclosed and claimed. | 12-31-2015 |
20150378808 | Techniques for Handling Errors in Persistent Memory - Examples may include a basic input/output system (BIOS) for a computing platform communicating with a controller for a non-volatile dual in-line memory module (NVDIMM). Communication between the BIOS and the controller may include a request for the controller to scan and identify error locations in non-volatile memory at the NVDIMM. The non-volatile memory may be capable of providing persistent memory for the NVDIMM. | 12-31-2015 |