Patent application number | Description | Published |
20090250733 | PIXEL SENSOR WITH REDUCED IMAGE LAG - A tensile-stress-generating structure is formed above a gate electrode in a CMOS image sensor to apply a normal tensile stress between a charge collection well of a photodiode, which is also a source region of a transfer transistor, and a floating drain in the direction connecting the source region and the floating drain. The tensile stress lowers the potential barrier between the source region and the body of the transfer transistor to effect a faster and more through transfer of the electrical charges in the source region to the floating drain. Image lag is thus reduced in the CMOS image sensor. Further, charge capacity of the source region is also enhanced due to the normal tensile stress applied to the source region. | 10-08-2009 |
20090309143 | PIXEL SENSOR CELL, METHODS AND DESIGN STRUCTURE INCLUDING OPTICALLY TRANSPARENT GATE - A pixel sensor cell, a method for fabricating or operating the pixel sensor cell and a design structure for fabricating the pixel sensor cell each include a semiconductor substrate that includes a photoactive region separated from a floating diffusion region by a channel region. At least one gate dielectric is located upon the semiconductor substrate at least in-part interposed between the photoactive region and the floating diffusion region, and at least one optically transparent gate is located upon the gate dielectric and at least in-part over the channel region. Preferably, the at least one gate dielectric is also located over the photoactive region and the at least one optically transparent gate is also located at least in-part over the photoactive region, to provide enhanced charge transfer capabilities within the pixel sensor cell, which is typically a CMOS pixel sensor cell. | 12-17-2009 |
20090311822 | PIXEL SENSOR CELL, METHODS AND DESIGN STRUCTURE INCLUDING OPTICALLY TRANSPARENT GATE - A pixel sensor cell, a method for fabricating or operating the pixel sensor cell and a design structure for fabricating the pixel sensor cell each include a semiconductor substrate that includes a photoactive region separated from a floating diffusion region by a channel region. At least one gate dielectric is located upon the semiconductor substrate at least in-part interposed between the photoactive region and the floating diffusion region, and at least one optically transparent gate is located upon the gate dielectric and at least in-part over the channel region. Preferably, the at least one gate dielectric is also located over the photoactive region and the at least one optically transparent gate is also located at least in-part over the photoactive region, to provide enhanced charge transfer capabilities within the pixel sensor cell, which is typically a CMOS pixel sensor cell. | 12-17-2009 |
20100013972 | PIXEL SENSOR CELL WITH FRAME STORAGE CAPABILITY - A set of frame transfer transistors are provided between a hold gate transistor and a transfer gate transistor of a CMOS image sensor to enable storage of charge generate in the photosensitive diode after exposure. The readout of the charges from the set of frame transfer transistors may be performed after a plurality of exposures of the CMOS image sensor, between each of which charges are shifted toward the transfer gate transistor within the set of frame transfer transistors. Useful operation modes are enabled including a burst mode operation for rapid capture of successive images and high dynamic range operations in which multiple images are taken with different exposure times or a large capacitance is provided by ganging the diffusions of the set of frame transfer transistors. | 01-21-2010 |
20100013973 | PIXEL SENSOR CELL WITH FRAME STORAGE CAPABILITY - A set of frame transfer transistors are provided between a hold gate transistor and a transfer gate transistor of a CMOS image sensor to enable storage of charge generate in the photosensitive diode after exposure. The readout of the charges from the set of frame transfer transistors may be performed after a plurality of exposures of the CMOS image sensor, between each of which charges are shifted toward the transfer gate transistor within the set of frame transfer transistors. Useful operation modes are enabled including a burst mode operation for rapid capture of successive images and high dynamic range operations in which multiple images are taken with different exposure times or a large capacitance is provided by ganging the diffusions of the set of frame transfer transistors. | 01-21-2010 |
20120037967 | CMOS PIXEL SENSOR CELLS WITH POLY SPACER TRANSFER GATES AND METHODS OF MANUFACTURE - CMOS pixel sensor cells with spacer transfer gates and methods of manufacture are provided herein. The method includes forming a middle gate structure on a gate dielectric. The method further includes forming insulation sidewalls on the middle gate structure. The method further includes forming spacer transfer gates on the gate dielectric on opposing sides of the middle gate, adjacent to the insulation sidewalls which isolate the middle gate structure from the spacer transfer gates. The method further includes forming a photo-diode region in electrical contact with one of the spacer transfer gates and a floating diffusion in electrical contact with another of the spacer transfer gates. | 02-16-2012 |