Patent application number | Description | Published |
20080281896 | INDUSTRIAL CONTROLLER - A first arithmetic operator ( | 11-13-2008 |
20090167191 | LIGHT EMITTING DEVICE - A light emitting device 1 is adapted, with a distributed power supply voltage, to turn on a light emitter 7, while timing a continuous conduction time with a pulse generating circuit 2, a frequency dividing circuit 3, and a counting memory circuit 4, to flash the light emitter 7 on and off with an on-off pattern depending on a result of the timing, signaling out information on the continuous conduction time. | 07-02-2009 |
20100251055 | PCI.EXPRESS COMMUNICATION SYSTEM AND COMMUNICATION METHOD THEREOF - When a transaction layer circuit detects an error, error information in respect of transmission data is set in a TLP digest. The method includes: a step in which, at an endpoint ( | 09-30-2010 |
20120030402 | PCI EXPRESS TLP PROCESSING CIRCUIT AND RELAY DEVICE PROVIDED WITH THIS - A PCI Express TLP processing circuit ( | 02-02-2012 |
20120047406 | REDUNDANCY CONTROL SYSTEM AND METHOD OF TRANSMITTING COMPUTATIONAL DATA THEREOF - A method of transmitting computational data comprising: a step of generating first computational data and generating first generated data using a first generation algorithm for error detection on return; a step of generating second computational data and generating second generated data using a second generation algorithm for error detection; a step of mutually comparing the first/second computational data; a step of transmitting transmission data including coincident computational data and first/second generated data; in the receiving device, a step of generating computational data and third/fourth generated data from preset first/second generation algorithms; and a step of comparing the first/third generated data and the first/third generated data, and detecting error in the received computational data. | 02-23-2012 |
20120096467 | MICROPROCESSOR OPERATION MONITORING SYSTEM - A microprocessor operation monitoring system whose own tasks are constituted by associating beforehand the task number of the task that is next to be started up, for each of the tasks constituting the program, and abnormality of microprocessor operation is detected by comparing and determining whether or not the announced task and the task to be started up match. | 04-19-2012 |
20120163239 | DOUBLE-RING NETWORK SYSTEM, METHOD FOR DETERMINING TRANSMISSION PRIORITY IN DOUBLE-RING NETWORK AND TRANSMISSION STATION DEVICE - According to one embodiment, in a double-ring network, a master station includes a transmitting and receiving permission switch portion, a communication port A at an A-system side, a communication port B at a B-system side, a first receiving control circuit portion, a transmitting and receiving control circuit portion, a frame detection determining circuit portion, a frame data generating circuit portion, a logical address determining circuit portion, a live list setting circuit portion and an address list setting circuit portion. The master station determines a token order (a transmission priority, also called a logical address) using a shortest path function by the logical address determining circuit portion and the address list setting circuit portion such that the token order does not depend on physical addresses of transmission stations and is matched to a connection order of transmission stations to realize path optimization. This reduces a transmission time. | 06-28-2012 |
20140050121 | DOUBLE-RING NETWORK SYSTEM, METHOD FOR DETERMINING TRANSMISSION PRIORITY IN DOUBLE-RING NETWORK AND TRANSMISSION STATION DEVICE - According to one embodiment, in a double-ring network, a master station includes a transmitting and receiving permission switch portion, a communication port A at an A-system side, a communication port B at a B-system side, a first receiving control circuit portion, a transmitting and receiving control circuit portion, a frame detection determining circuit portion, a frame data generating circuit portion, a logical address determining circuit portion, a live list setting circuit portion and an address list setting circuit portion. The master station determines a token order (a transmission priority, also called a logical address) using a shortest path function by the logical address determining circuit portion and the address list setting circuit portion such that the token order does not depend on physical addresses of transmission stations and is matched to a connection order of transmission stations to realize path optimization. This reduces a transmission time. | 02-20-2014 |