Patent application number | Description | Published |
20100213301 | Shredder Hammers Including Improved Engagement Between the Hammer Pin and the Hammer - Shredder hammers include a hammer pin opening in which at least some portion of the interior surface is curved in a direction moving from one major surface of the shredder hammer to the other. This interior surface may be smoothly formed as an arc of a circle, as a parabola, as a hyperbola, or as another curved surface, with the local extrema within the interior of the hole (e.g., at or near the center). Providing the curved interior surface helps vary and disperse the locations where force is absorbed due to contact between the hammer pin and the walls defining the hammer pin opening when the shredding hammer blade contacts the material to be shredded. Other structures include engagement between the hammer pin and the hammer as part of a bushing member, a spool or sleeve member, or a ball swivel member. | 08-26-2010 |
20130233955 | SHREDDER HAMMERS - Shredder hammers having first and second major surfaces on opposing sides, and a circumferential edge. The hammer includes a mounting portion and a working portion. The mounting portion defines a mounting aperture that extends from the first major surface to the second major surface, and is configured to receive a hammer mounting pin. The working portion includes at least one recess in at least one of the first and second major surfaces with opposed walls that extend away from a distal portion of the circumferential edge. The hammers are used in shredding systems for shredding material. | 09-12-2013 |
20140151475 | HAMMER FOR SHREDDING MACHINES - Shredder hammers having first and second major surfaces on opposing sides, and a circumferential edge. A mounting portion includes a mounting hole that extends from the first major surface to the second major surface, and is configured to receive a hammer mounting pin for mounting in a reducing system. The circumferential edge includes a primary impact face to initially impact materials to be reduced and a wear edge to subsequently crush and shear the material against a wall of the equipment. The hammer is biased forward on the pin to admit more material to be crushed between the wear edge and the grates. | 06-05-2014 |
20140299689 | Discharge Grates For Reduction Mills - Discharge grates and grate components of reducing equipment have reduced amounts of material to provide lower costs, lower weight, and less scrap while still providing adequate resistance to bending, deflection, and/or warping and suitable material discharge. | 10-09-2014 |
Patent application number | Description | Published |
20100231635 | System And Method For Evaluating And Correcting Image Quality In An Image Generating Device - A system evaluates image quality in an image generating system in a manner that accounts for the interaction of the calibration tools used to evaluate and correct image quality in the image generating system. The system includes a test pattern generator configured to generate an image with an image generating system, an image capture device configured to generate a digital signal corresponding to the generated test pattern, an image evaluator configured to process the digital signal to detect and correct anomalies detected in the generated test pattern, a plurality of calibration tools, each calibration tool being comprised of at least one test pattern, at least one set of detection criteria, and at least one set of anomaly correction parameters, and a controller configured to select the calibration tools for operation of the test pattern generator and the image evaluator in accordance with a predetermined sequence that attenuates changes arising from application of correction parameters of one calibration tool upon a later selected calibration tool. | 09-16-2010 |
20120120144 | System And Method For Evaluating And Correcting Image Quality In An Image Generating Device - A system evaluates image quality in an image generating system. The system includes a test pattern generator configured to generate an image with an image generating system, an image capture device configured to generate a digital signal corresponding to the generated test pattern, an image evaluator configured to process the digital signal to detect and correct anomalies detected in the generated test pattern, a plurality of calibration tools, each calibration tool being comprised of at least one test pattern, at least one set of detection criteria, and at least one set of anomaly correction parameters, and a controller configured to select the calibration tools for operation of the test pattern generator and the image evaluator in accordance with a predetermined sequence that attenuates changes arising from application of correction parameters of one calibration tool upon a later selected calibration tool. | 05-17-2012 |
Patent application number | Description | Published |
20090011565 | Field effect transistor structure with abrupt source/drain junctions - Microelectronic structures embodying the present invention include a field effect transistor (FET) having highly conductive source/drain extensions. Formation of such highly conductive source/drain extensions includes forming a passivated recess which is back filled by epitaxial deposition of doped material to form the source/drain junctions. The recesses include a laterally extending region that underlies a portion of the gate structure. Such a lateral extension may underlie a sidewall spacer adjacent to the vertical sidewalls of the gate electrode, or may extend further into the channel portion of a FET such that the lateral recess underlies the gate electrode portion of the gate structure. In one embodiment the recess is back filled by an in-situ epitaxial deposition of a bilayer of oppositely doped material. In this way, a very abrupt junction is achieved that provides a relatively low resistance source/drain extension and further provides good off-state subthreshold leakage characteristics. Alternative embodiments can be implemented with a back filled recess of a single conductivity type. | 01-08-2009 |
20090174070 | Three-dimensional stacked substrate arrangements - Three-dimensional stacked substrate arrangements with reliable bonding and inter-substrate protection. | 07-09-2009 |
20100133595 | FIELD EFFECT TRANSISTOR STRUCTURE WITH ABRUPT SOURCE/DRAIN JUNCTIONS - Microelectronic structures embodying the present invention include a field effect transistor (FET) having highly conductive source/drain extensions. Formation of such highly conductive source/drain extensions includes forming a passivated recess which is back filled by epitaxial deposition of doped material to form the source/drain junctions. The recesses include a laterally extending region that underlies a portion of the gate structure. Such a lateral extension may underlie a sidewall spacer adjacent to the vertical sidewalls of the gate electrode, or may extend further into the channel portion of a FET such that the lateral recess underlies the gate electrode portion of the gate structure. In one embodiment the recess is back filled by an in-situ epitaxial deposition of a bilayer of oppositely doped material. In this way, a very abrupt junction is achieved that provides a relatively low resistance source/drain extension and further provides good off-state subthreshold leakage characteristics. Alternative embodiments can be implemented with a back filled recess of a single conductivity type. | 06-03-2010 |
20110147059 | Substrate for integrated circuit devices including multi-layer glass core and methods of making the same - Disclosed are embodiments of a substrate for an integrated circuit (IC) device. The substrate includes a core comprised of two or more discrete glass layers that have been bonded together. A separate bonding layer may be disposed between adjacent glass layers to couple these layers together. The substrate may also include build-up structures on opposing sides of the multi-layer glass core, or perhaps on one side of the core. Electrically conductive terminals may be formed on both sides of the substrate, and an IC die may be coupled with the terminals on one side of the substrate. The terminals on the opposing side may be coupled with a next-level component, such as a circuit board. One or more conductors extend through the multi-layer glass core, and one or more of the conductors may be electrically coupled with the build-up structures disposed over the core. Other embodiments are described and claimed. | 06-23-2011 |
20110247872 | DEBOND INTERCONNECT STRUCTURES - The present subject matter relates to the field of fabricating microelectronic devices. In at least one embodiment, the present subject matter relates to forming an interconnect that has a portion thereof which becomes debonded from the microelectronic device during cooling after attachment to an external device. The debonded portion allows the interconnect to flex and absorb stress. | 10-13-2011 |
20110260319 | THREE-DIMENSIONAL STACKED SUBSTRATE ARRANGEMENTS - Three-dimensional stacked substrate arrangements with reliable bonding and inter-substrate protection. | 10-27-2011 |
20120280387 | THREE-DIMENSIONAL STACKED SUBSTRATE ARRANGEMENTS - Three-dimensional stacked substrate arrangements with reliable bonding and inter-substrate protection. | 11-08-2012 |
20140106560 | DEBOND INTERCONNECT STRUCTURES - The present subject matter relates to the field of fabricating microelectronic devices. In at least one embodiment, the present subject matter relates to forming an interconnect that has a portion thereof which becomes debonded from the microelectronic device during cooling after attachment to an external device. The debonded portion allows the interconnect to flex and absorb stress. | 04-17-2014 |
20140264739 | METHODS OF FORMING UNDER DEVICE INTERCONNECT STRUCTURES - Methods of forming microelectronic interconnect under device structures are described. Those methods and structures may include forming a device layer in a first substrate, forming at least one routing layer in a second substrate, and then coupling the first substrate with the second substrate, wherein the first substrate is bonded to the second substrate. | 09-18-2014 |