Patent application number | Description | Published |
20090034536 | METHOD AND SYSTEM FOR LOCALISING USERS FOR SERVICES BASED ON SIP OR H.323 PROTOCOLS WITH DYNAMIC IP ADDRESS ALLOCATION - The aim of the invention is to localise a terminal ( | 02-05-2009 |
20110230190 | METHOD OF MANAGING A USER TERMINAL IN A TELECOMMUNICATIONS NETWORK, AND AN ASSOCIATED DEVICE - A method and apparatus are provided for managing a terminal of a user of a telecommunications network. The terminal is connected to the telecommunications network via at least one access network. The method includes a step, executed on receiving a registration request including an address of record of the user, an address of contact of the terminal, and an access network type of the terminal, of storing in a database an association between the address of record of the user, the access network type of the terminal, and the address of contact of the terminal. | 09-22-2011 |
20120096529 | Method and Device for Managing Authentication of a User - A method and apparatus are provided for managing authentication of a user of a telecommunications network of an operator. The method includes the following steps: on receipt of a request for access to a service provided by the operator of this network by the user, issuing a request for identification of an authentication server destined for an authentication location server, the request including at least one identifier of the user; and on receipt of a response comprising an identifier of an authentication server associated with the identifier of the user, issuing a request for authentication of the user at the server identified for the requested service. | 04-19-2012 |
20120282910 | Management of a Wireless Communication Interface of a Terminal - The management method of the invention comprises: an obtaining step (E | 11-08-2012 |
20140033282 | PUTTING IN PLACE A SECURITY ASSOCIATION OF GBA TYPE FOR A TERMINAL IN A MOBILE TELECOMMUNICATIONS NETWORK - A method is provided for putting in place a security association of GBA type for a terminal. The method includes the following steps, executed in a network access server, following receipt of a request for attachment to the network from the terminal: dispatching a request for association of security to a priming function server; reception of a response comprising security association parameters, from the priming function server and dispatching a message including the security association parameters to the terminal. | 01-30-2014 |
20140096192 | PUTTING IN PLACE A SECURITY ASSOCIATION OF GBA TYPE FOR A TERMINAL IN A MOBILE TELECOMMUNICATIONS NETWORK - A method is provided for putting in place a security association of GBA type for a terminal. The method includes the following steps, executed in a network access server, following the receipt of a request for attachment to the network from the terminal: dispatching a request to a subscriber server, receipt of a response including an indication that the user profile associated with the terminal supports the security association of GBA type. | 04-03-2014 |
20150087286 | METHOD OF MANAGING AT LEAST ONE WIRELESS COMMUNICATIONS INTERFACE OF A TERMINAL, AND A TERMINAL - A method of managing at least one wireless communications interface of a terminal by performing an obtaining step (E | 03-26-2015 |
Patent application number | Description | Published |
20130078082 | TURBOCHARGER VARIABLE-NOZZLE ASSEMBLY WITH VANE SEALING ARRANGEMENT - A variable-nozzle assembly for a turbocharger includes a generally annular nozzle ring and an array of vanes rotatably mounted to the nozzle ring such that the vanes can be pivoted about their axes for regulating exhaust gas flow to the turbine wheel. A unison ring engages vane arms that are affixed to axles of the vanes, such that rotation of the unison ring causes the vanes to pivot between a closed position and an open position. The vanes have proximal ends that are adjacent a face of the nozzle ring. A vane sealing member is supported on the nozzle ring and has a portion disposed between the proximal ends of the vanes and the face of the nozzle ring. The unison ring includes cams that engage cam followers. Rotational movement of the unison ring causes the cam followers to be moved axially and thereby urge the vane sealing member against the proximal ends of the vanes. | 03-28-2013 |
20130078083 | TURBOCHARGER WITH VARIABLE NOZZLE HAVING LABYRINTH SEAL FOR VANES - A variable nozzle for a turbocharger includes a plurality of vanes rotatably mounted on a nozzle ring and disposed in a nozzle flow path defined between the nozzle ring and an opposite nozzle wall. Either or both of the faces of the nozzle ring and nozzle wall include(s) grooves extending substantially transverse to a general flow direction of the flow through the nozzle, and there are clearances between the ends of the vanes and the adjacent faces. Leakage flow through the clearance between the end of each vane and the adjacent face having the grooves must proceed across the grooves, and thus a labyrinthine flow passage is presented to the leakage flow. The labyrinthine passage has a greater resistance to flow than would be the case without the grooves. Accordingly, leakage flow is reduced, which is beneficial to turbine efficiency. | 03-28-2013 |
20130195629 | CONTACTING VANES - An assembly can include vanes and a base configured to seat the vanes at a radial distance about an axis where each vane includes a leading edge and a trailing edge, a pair of lateral surfaces that meet at the leading edge and at the trailing edge, an extension that extends from one of the lateral surfaces and that has a contact surface, and a stop surface to form a contact with a contact surface of another vane to define a minimum flow distance between the vane and the other vane. Various other examples of devices, assemblies, systems, methods, etc., are also disclosed. | 08-01-2013 |
20140134015 | Turbocharger and Variable-Nozzle Cartridge Therefor - A variable-vane assembly for a turbocharger includes an annular nozzle ring supporting an array of rotatable vanes, an insert having a tubular portion sealingly received into the bore of the turbine housing and having a nozzle portion extending radially out from one end of the tubular portion and being axially spaced from the nozzle ring with the vanes therebetween, and an annular retainer ring disposed radially outward of the nozzle ring and extending generally radially inwardly. The nozzle ring's face is stepped, and a radially inner edge of the retainer ring engages the face of the nozzle ring radially outward of the step, the radially inner edge of the retainer ring having an axial thickness that is less than the step height such that a remaining portion of the step is presented to the exhaust gas flowing through the nozzle. | 05-15-2014 |
Patent application number | Description | Published |
20080197447 | METHOD FOR MANUFACTURING A STRUCTURE OF SEMICONDUCTOR-ON-INSULATOR TYPE - A method for manufacturing an insulated semiconductor layer, including: forming a porous silicon layer on a single-crystal silicon surface; depositing an insulating material so that it penetrates into the pores of the porous silicon layer; eliminating the insulating material to expose the upper surface of the porous silicon; and growing by epitaxy a semiconductor layer. | 08-21-2008 |
20080246121 | METHOD OF FABRICATING A DEVICE WITH A CONCENTRATION GRADIENT AND THE CORRESPONDING DEVICE - A semiconductive device is fabricated by forming, within a semiconductive substrate, at least one continuous region formed of a material having a non-uniform composition in a direction substantially perpendicular to the thickness of the substrate. | 10-09-2008 |
20090127584 | Transistor with a germanium-based channel encased by a gate electrode and method for producing one such transistor - Source and drain electrodes are each formed by an alternation of first and second layers made from a germanium and silicon compound. The first layers have a germanium concentration comprised between 0% and 10% and the second layers have a germanium concentration comprised between 10% and 50%. At least one channel connects two second layers respectively of the source electrode and drain electrode. The method comprises etching of source and drain zones, connected by a narrow zone, in a stack of layers. Then superficial thermal oxidation of said stack is performed so a to oxidize the silicon of the germanium and silicon compound having a germanium concentration comprised between 10% and 50% and to condense the germanium Ge. The oxidized silicon of the narrow zone is removed and a gate dielectric and a gate are deposited on the condensed germanium of the narrow zone. | 05-21-2009 |
20100035414 | METHOD FOR PREPARING A GERMANIUM LAYER FROM A SILICON-GERMANIUM-ON-ISOLATOR SUBSTRATE - A method for making a germanium-on-insulator layer from an SGOI substrate, including: a) depositing on the substrate a layer of a metallic element M capable of selectively forming a silicide, the layer being in contact with a silicon-germanium alloy layer; and b) a reaction between the alloy layer and the layer of a metallic element M, by which a stack of M silicide-germanium-insulator layers is obtained. Such a method may, for example, find application to production of electronic devices such as MOSFET transistors. | 02-11-2010 |
20100227125 | METHOD TO FABRICATE A MOULD FOR LITHOGRAPHY BY NANO-IMPRINTING - The invention concerns a nano-imprinting device with three dimensions characterized in that it comprises at least:
| 09-09-2010 |
20120021606 | PROCESS FOR PRODUCING TWO INTERLEAVED PATTERNS ON A SUBSTRATE - A process for producing two interleaved patterns on a substrate uses photolithography and etching to produce, on the substrate, a first pattern of first material protruding regions separated by recessed regions. A non-conformal deposition of a second material on the first pattern forms cavities in the recessed regions of the first pattern. These cavities are opened and filled with a third material. The second material is then removed, and the remaining third material forms a second pattern of third material protruding regions, wherein the second pattern is interleaved with the first pattern. | 01-26-2012 |
20120115311 | METHOD FOR FORMING A MULTILAYER STRUCTURE - The method for forming a multilayer structure on a substrate comprises providing a stack successively comprising an electron hole blocking layer, a first layer made from N-doped semiconductor material having a dopant concentration greater than or equal to 10 | 05-10-2012 |
20120153394 | METHOD FOR MANUFACTURING A STRAINED CHANNEL MOS TRANSISTOR - A method for manufacturing a strained channel MOS transistor including the steps of: forming, at the surface of a semiconductor substrate, a MOS transistor comprising source and drain regions and an insulated sacrificial gate which partly extends over insulation areas surrounding the transistor; forming a layer of a dielectric material having its upper surface level with the upper surface of the sacrificial gate; removing the sacrificial gate; etching at least an upper portion of the exposed insulation areas to form trenches therein; filling the trenches with a material capable of applying a strain to the substrate; and forming, in the space left free by the sacrificial gate, an insulated MOS transistor gate. | 06-21-2012 |
20130196500 | METHOD FOR FORMING A VIA CONTACTING SEVERAL LEVELS OF SEMICONDUCTOR LAYERS - A method for forming a via connecting a first upper level layer to a second lower level layer, both layers being surrounded with an insulating material, the method including the steps of: a) forming an opening to reach an edge of the first layer, the opening laterally continuing beyond said edge; b) forming a layer of a protection material on said edge only; c) deepening said opening by selectively etching the insulating material to reach the second lower level layer; and d) filling the opening with at least one conductive contact material. | 08-01-2013 |
20130252412 | PROCESS FOR PRODUCING AN INTEGRATED CIRCUIT - A process for producing an integrated circuit on the surface of a substrate, the process including: producing a first layer, including active zones and insulating zones, on the surface of the substrate; producing gate zones on the surface of the first layer, the gate zones each being surrounded by insulating spacers; producing source/drain electrodes; producing a dielectric layer between the insulating spacers, the dielectric layer having an upper surface level with the upper surfaces of the gate zones; partially etching each gate zone so as to lower the upper surface of a first part of each gate zone; and depositing an insulating dielectric layer on the first parts of the gate zones. | 09-26-2013 |
20130273722 | CONTACT ON A HETEROGENEOUS SEMICONDUCTOR SUBSTRATE - A method for producing a microelectronic device with plural zones made of a metal and semiconductor compound, from semiconductor zones made of different semiconductor materials, and on which a thin semiconductor layer is formed prior to the deposition of a metal layer so as to lower the nucleation barrier of the semiconductor zones when reacting with the metal layer. | 10-17-2013 |
20130295734 | METHOD FOR FORMING GATE, SOURCE, AND DRAIN CONTACTS ON A MOS TRANSISTOR - A method for forming gate, source, and drain contacts on a MOS transistor having an insulated gate including polysilicon covered with a metal gate silicide, this gate being surrounded with at least one spacer made of a first insulating material, the method including the steps of a) covering the structure with a second insulating material and leveling the second insulating material to reach the gate silicide; b) oxidizing the gate so that the gate silicide buries and covers the a silicon oxide; c) selectively removing the second insulating material; and d) covering the structure with a first conductive material and leveling the first conductive material all the way to a lower level at the top of the spacer. | 11-07-2013 |
20140027886 | METHOD OF FABRICATING A DEVICE WITH A CONCENTRATION GRADIENT AND THE CORRESPONDING DEVICE - A semiconductive device is fabricated by forming, within a semiconductive substrate, at least one continuous region formed of a material having a non-uniform composition in a direction substantially perpendicular to the thickness of the substrate. | 01-30-2014 |
20140217520 | AIR-SPACER MOS TRANSISTOR - A MOS transistor including, above a gate insulator, a conductive gate stack having a height, a length, and a width, this stack having a lower portion close to the gate insulator and an upper portion, wherein the stack has a first length in its lower portion, and a second length shorter than the first length in its upper portion. | 08-07-2014 |
20140246723 | METHOD FOR MANUFACTURING A FIN MOS TRANSISTOR - A method for manufacturing a fin MOS transistor from an SOI-type structure including a semiconductor layer on a silicon oxide layer coating a semiconductor support, this method including the steps of: a) forming, from the surface of the semiconductor layer, at least one trench delimiting at least one fin in the semiconductor layer and extending all the way to the surface of the semiconductor support; b) etching the sides of a portion of the silicon oxide layer located under the fin to form at least one recess under the fin; and c) filling the recess with a material selectively etchable over silicon oxide. | 09-04-2014 |
20140326955 | PLANAR TRANSISTORS WITH NANOWIRES COINTEGRATED ON A SOI UTBOX SUBSTRATE - Fabrication of a microelectronic device on a semiconductor on insulator type substrate, the device being provided with a transistor of a given type, the channel structure of which is formed from semiconducting bar(s), a dielectric area different from the insulating layer of the substrate being provided to replace the insulating layer, facing the transistor channel structure, specifically for this given type of transistor. | 11-06-2014 |
20140335663 | METHOD OF MAKING A TRANSITOR - A method for manufacturing a transistor includes forming a stack of semiconductor on insulator type layers including at least one substrate, surmounted by a first insulating layer and an active layer to form a channel for the transistor; forming a gate stack on the active layer; producing a source and a drain including forming, on either side of the gate stack, cavities by at least one step of etching the active layer, the first insulating layer, and part of the substrate selectively to the gate stack to remove the active layer, the first insulating layer, and a portion of the substrate outside regions situated below the gate stack; forming a second insulating layer on the bared surfaces of the substrate, to form a continuous insulating layer with the first insulating layer; baring of the lateral ends of the channel; and the filling of the cavities by epitaxy. | 11-13-2014 |
20140349460 | Method for producing a silicon-germanium film with variable germanium content - The substrate is provided with a first semiconducting area partially covered by a first masking pattern to define a protected surface and an open surface. A continuous layer of silicon-germanium is deposited in non-selective manner on the first semiconducting area and on the first gate pattern. The continuous silicon-germanium layer forms an interface with the first semiconducting area. A diffusion/condensation annealing is performed to make the germanium atoms diffuse from the silicon-germanium layer to the open surface of the first semiconducting area. The masking pattern is a gate stack of the transistor or is used to define the shape of the gate stack in an electrically insulating layer so as to form a self-aligned gate stack with the source and drain areas. | 11-27-2014 |
20140370666 | METHOD OF MAKING A SEMICONDUCTOR LAYER HAVING AT LEAST TWO DIFFERENT THICKNESSES - A method is provided for producing a semiconductor layer having at least two different thicknesses from a stack of the semiconductor on insulator type including at least one substrate on which an insulating layer and a first semiconductor layer are successively disposed, the method including etching the first layer so that said layer is continuous and includes at least one first region having a thickness less than that of at least one second region; oxidizing the first layer to form an electrically insulating oxide film on a surface thereof so that, in the first region, the oxide film extends as far as the insulating layer; partly removing the oxide film to bare the first layer outside the first region; forming a second semiconductor layer on the stack, to form, with the first layer, a third continuous semiconductor layer having a different thickness than that of the first and second regions. | 12-18-2014 |
20140370668 | METHOD OF MAKING A TRANSITOR - The invention relates to a method for manufacturing a transistor comprising the preparation of a stack of layers of the semiconductor on insulator type comprising at least one substrate on which an insulating layer and an initial semiconductor layer are successively disposed. The method includes the formation of at least one oxide pad extending from a top face of the insulating layer, the formation of an additional layer made from semiconductor material covering the oxide pad and intended to form a channel for the transistor, the formation of a gate stack above the oxide pad, and the formation of a source and drain on either side of the gate stack. | 12-18-2014 |