Patent application number | Description | Published |
20090027490 | IMAGE PROCESSING APPARATUS FOR ENDOSCOPE - This is an endoscope apparatus which has an endoscope which picks up an image of a sample using a solid state image pickup element and outputs an image pickup signal, and a processor which processes the above-mentioned image pickup signal, generates HDTV and SDTV serial digital video signals, switches one side of those selectively, and performs a serial output, in which the serial digital video signal switched selectively by the above-mentioned processor is output through a first connector, the above-mentioned processor is equipped with a discrimination signal generating section which is linked with selection switching of the above-mentioned HDTV or SDTV serial digital video signal to generate an HDTV/SDTV discrimination signal which can discriminate the above-mentioned HDTV or SDTV serial digital video signal, and the discrimination signal is output through a second connector different from the above-mentioned first connector. | 01-29-2009 |
20100331624 | ENDOSCOPE SYSTEM AND ENDOSCOPIC IMAGE PROCESSING APPARATUS - An endoscope system includes: an endoscope equipped with an insertion portion, and an image pickup unit disposed at a distal end portion of the insertion portion; an illumination unit detachably connected to the endoscope; an imaging mode input unit used to set an imaging mode of the endoscope to one of a normal-light mode and a special-light mode; a processing condition selection unit which selects a processing condition for a color correction process of an endoscopic image based on the imaging mode; and a processor detachably connected to the endoscope and equipped with an image processing unit which performs the color correction process, under the processing condition selected by the processing condition selection unit, with respect to each of hue regions partitioned by at least eight reference color axes including six reference color axes which divide a color space into R (red), M (magenta), B (blue), C (cyan), G (green), and Y (yellow) hue regions and at least two reference color axes established additionally based on the imaging mode. | 12-30-2010 |
Patent application number | Description | Published |
20160032227 | CLEANING COMPOSITION FOR SEMICONDUCTOR SUBSTRATE AND CLEANING METHOD - A cleaning composition for a semiconductor substrate contains a solvent, and a polymer that includes a fluorine atom, a silicon atom or a combination thereof. The content of water in the solvent is preferably no greater than 20% by mass. The cleaning composition preferably further contains an organic acid which is a non-polymeric acid. The organic acid is preferably a polyhydric carboxylic acid. The acid dissociation constant of the polymer is preferably less than that of the organic acid. The solubility of the organic acid in water at 25° C. is preferably no less than 5% by mass. The organic acid is preferably a solid at 25° C. | 02-04-2016 |
20160035561 | SUBSTRATE PROCESSING SYSTEM, SUBSTRATE CLEANING METHOD, AND RECORDING MEDIUM - An object of the present invention is to obtain a high removing performance of particles. The substrate processing system according to the exemplary embodiment comprises a holding unit and a removing solution supply unit. The holding unit holds a substrate that has a treatment film formed thereon, wherein the treatment film comprises an organic solvent and a fluorine-containing polymer that is soluble in the organic solvent. The removing solution supply unit supplies to the treatment film formed on the substrate, a removing solution capable of removing the treatment film. | 02-04-2016 |
20160035564 | SUBSTRATE CLEANING METHOD AND RECORDING MEDIUM - An object of the present invention is to be able to obtain a high removing performance of particles. The substrate processing method according to the exemplary embodiment comprises a film-forming treatment solution supply step and a removing solution supply step. The film-forming treatment solution supply step comprising supplying to a substrate, a film-forming treatment solution containing an organic solvent and a fluorine-containing polymer that is soluble in the organic solvent is supplied. The removing solution supply step comprises supplying to a treatment film formed by solidification or curing of the film-forming treatment solution on the substrate, a removing solution capable of removing the treatment film. | 02-04-2016 |
Patent application number | Description | Published |
20090070458 | SERVER DEVICE, INFORMATION REPORT METHOD, AND INFORMATION REPORT SYSTEM - A server device including a management unit for receiving and managing a status of equipment or a user operating the equipment as status information and detecting a load status of the server device from receiving situation of the status information, a notification request receiving unit for receiving a notification request message that requests notification of the status information from a reference person terminal; a notification response transmitting unit for transmitting a notification respond message that responds to the received notification request message; and a status notification transmitting unit for transmitting an information notification message including the status information received by the management unit to the reference person terminal according to the load status. The server device can precisely transmit information from a user device, and the like, to the reference person terminal when the server device is in an overload state. | 03-12-2009 |
20100262669 | CONNECTION DEVICE, CONNECTION METHOD FOR THE SAME, AND PROGRAM - A connection device according to an aspect of the present invention is a server ( | 10-14-2010 |
20100274909 | CONNECTION DEVICE AND CONNECTION METHOD - A connection device that does not require complicated operation by a user an interconnects a single-display conference terminal and the multi-display conference terminal includes an address holding unit ( | 10-28-2010 |
20110254913 | CONFERENCING APPARATUS AND COMMUNICATION SETTING METHOD - A conferencing apparatus that is adapted to facilitate a video conference includes a first address information acquisition unit that acquires address information of a first processing terminal device which is connected to a first conferencing apparatus via a first local area network, a first address information notification unit that notifies both the address information of the first conferencing apparatus and the address information of the first processing terminal device to a second conferencing apparatus currently communicating with the first conferencing apparatus, and a first address information reception unit that receives at least address information of the second conferencing apparatus transmitted from the second conferencing apparatus. When the first conferencing apparatus receives a request message of start of sharing from the first processing terminal device, the first address information acquisition unit of the first conferencing apparatus acquires address information, and the first address information notification unit performs notification of the acquired address information. Therefore, conference materials can be output on display devices of the respective processing terminal devices of the participants in the video conference without requiring high level setting of the network. In addition, other participants can carry out interactive operations with respect to a material which is presented by a participant. | 10-20-2011 |
20120063360 | PATH SETTING DEVICE AND PATH SETTING METHOD - Disclosed is a path setting device capable of setting a distribution path of packets more speedily, when the originator of information is switched. The terminal ( | 03-15-2012 |
20120089680 | COMMUNICATION APPARATUS, COMMUNICATION SYSTEM AND SESSION CONTROL METHOD - A communication apparatus controls a session with respect to at least one other communication apparatus by using a basic method or a reply of a call control protocol. The communication apparatus includes a message receiving section that receives a message which is transmitted from the other communication apparatus, and the message in which reconnection control information related to an operation after an end of the session is described in the basic method or the reply, and a first controlling section that performs a reconnection control based on the reconnection control information contained in the message. | 04-12-2012 |
Patent application number | Description | Published |
20100149894 | Semiconductor memory device that can relief defective address - To comprise a memory cell array, a read amplifier that is provided outside the memory cell array and amplifies data read from the memory cell array, a write amplifier that is provided outside the memory cell array and amplifies data to be written in the memory cell array, and a relief storage cell that is provided outside the memory cell array and connected to an input terminal of the read amplifier and an output terminal of the write amplifier via a switch. With this configuration, a timing of operating a main amplifier and the relief storage cell does not need to be changed depending on a position of a memory block. Further, the number of components required for connecting to the relief storage cell can be minimized. | 06-17-2010 |
20120120747 | SEMICONDUCTOR DEVICE - A first data amplifier connects to a first memory cell identified by an X-address signal and a selection signal obtained by predecoding a Y-address signal. A second data amplifier connects to a second memory cell identified by the X-address signal and a delayed selection signal obtained by delaying the selection signal. A generator generates a delayed operation clock signal by delaying an operation clock signal of the first data amplifier. A timing controller receives a first control signal for controlling an operation of the first data amplifier and a second control signal for controlling an operation of the second data amplifier, outputs the first control signal to the first data amplifier at a timing according to the operation clock signal, and outputs the second control signal to the second data amplifier at a timing according to the delayed operation clock signal. | 05-17-2012 |
20120230141 | SEMICONDUCTOR DEVICE AND DATA PROCESSING SYSTEM - Disclosed herein is a semiconductor device comprising local bit lines, a global bit line, local switch control lines, main switch control lines, hierarchical switches controlling electrical connections between the local bit lines and the global bit line in response to potentials of the local switch control lines, local switch drivers driving the local switch control lines in response to potentials of the main switch control lines, and main switch drivers selectively activating the main switch control lines. | 09-13-2012 |
20130294137 | SEMICONDUCTOR DEVICE HAVING BIT LINE HIERARCHICALLY STRUCTURED - Disclosed herein is a semiconductor device that includes a plurality of memory cells; a local bit line coupled to the memory cells; a global bit line; and a first switch circuit coupled between the global bit line and the local bit line, the first switch circuit electrically connecting the local bit line to the global bit line when at least one of first and second control signals is in an active state, and the first switch circuit electrically disconnecting the local bit line to the global bit line when both of the first and second control signals are in an inactive state. | 11-07-2013 |
20130301330 | SEMICONDUCTOR DEVICE HAVING HIERARCHICAL BIT LINE STRUCTURE - A semiconductor device having hierarchical bit lines is disclosed, which comprises: a first global bit line; first and second local bit lines coupled in common to the first global bit line; first and second power lines; a first transistor coupled between the first local bit line and the first power line; a second transistor coupled between the second local bit line and the second power line; a third transistor coupled between the first and second power lines. | 11-14-2013 |
20130308403 | SEMICONDUCTOR DEVICE HAVING SENSE AMPLIFIER CIRCUIT - Disclosed herein is a device that includes: a first control element that controls an amount of current flowing between a second line and a first node according to a potential of a first line; a second control element that controls an amount of current flowing between the first line and the first node according to a potential of the second line; a first control circuit that performs a first operation to fix potentials of the first and second lines at a first potential; a second control circuit that performs a second operation to connect the first node to the second node; and a third control circuit that fixes a potential of the first node at a second potential after the first control circuit stops the first operation until the second control circuit starts the second operation. | 11-21-2013 |
20140050004 | SEMICONDUCTOR DEVICE HAVING HIERARCHICALLY STRUCTURED BIT LINES - Disclosed herein is a device includes first and second memory mats. The first memory mat includes first and defective memory cells and first local bit lines coupled to a first global bit line. Each of the first local bit lines is coupled to associated ones of the first memory cells, one of the first local bit lines is further coupled to the defective memory cell. The second memory mat includes second and redundant memory cells and second local bit lines coupled to a second global bit line. Each of the second local bit lines is coupled to associated ones of the second memory cells, one of the second local bit lines is further coupled to the redundant memory cell. The device further includes a control circuit accessing the redundant memory cell when the access address information coincides with the defective address information that designates the defective memory cell. | 02-20-2014 |
20140169058 | SEMICONDUCTOR DEVICE AND DATA PROCESSING SYSTEM - Disclosed herein is a semiconductor device comprising local bit lines, a global bit line, local switch control lines, main switch control lines, hierarchical switches controlling electrical connections between the local bit lines and the global bit line in response to potentials of the local switch control lines, local switch drivers driving the local switch control lines in response to potentials of the main switch control lines, and main switch drivers selectively activating the main switch control lines. | 06-19-2014 |
20150213876 | SEMICONDUCTOR DEVICE WITH FLOATING BODY STRUCTURE - A semiconductor device is disclosed, which comprises: a memory cell, first and second bit lines, a switch between the first and second bit lines, a sense amplifier, a sense amplifier driving circuit driving the sense amplifier with first and second voltages, a precharge circuit precharging the first bit line, and a control circuit. The control circuit performs a read operation so that the first and second bit lines are disconnected from each other and the first bit line is precharged to a precharge voltage, during a first period. Thereafter, the control circuit performs a restoring operation in a state where the first and second bit lines are connected to each other and the precharging of the first bit line is cancelled, during a second period after the first period. The sense amplifier is driven with the second voltage for increasing its driving ability during the second period | 07-30-2015 |
20150255146 | SEMICONDUCTOR DEVICE INCLUDING SUBWORD DRIVER CIRCUIT - The present invention is provided with: subword drivers SWD for driving subword lines SWL, a selection circuit for supplying either negative potential VKK | 09-10-2015 |