Patent application number | Description | Published |
20130021851 | ANTI-FUSE CIRCUIT AND METHOD FOR ANTI-FUSE PROGRAMMING AND TEST THEREOF - An anti-fuse circuit including a plurality of programmable units and a test module is provided. The programmable units receive a stress voltage, a program data, and a write enable signal. During a programming period, the programmable units sequentially transmit the program data. When the write enable signal is enabled, the stress voltage stresses the programmable units according to the program data, and the programmable units output programming results for test. The test module is coupled to the programmable units and receives the program data and the programming results. During a test period, the test module compares the programming results with the program data and outputs different logic levels according to a result of the comparison of the first programming results and the program data. A method for anti-fuse programming and test adapted to the foregoing anti-fuse circuit is also provided. | 01-24-2013 |
20130021854 | ANTI-FUSE CIRCUIT - An anti-fuse circuit including a programmable module, a read module, and a control module is provided. The programmable module has a plurality of data cells. The read module is coupled to the programmable module. During a normal operation, the read module distinguishes which one or more of the data cells are stressed. The control module is coupled to the programmable module. During a stress operation, the control module controls each stressed data cell to be coupled to a high voltage, a low voltage, and a control voltage. The first end of each stressed data cells is coupled to the low voltage, the second end of each stressed data cells is coupled to the high voltage, and the control end of each stressed data cells is coupled to the control voltage during the stress operation. | 01-24-2013 |
20130028029 | METHOD OF CONTROLLING OPERATIONS OF A DELAY LOCKED LOOP OF A DYNAMIC RANDOM ACCESS MEMORY - A method for controlling operations of a delay locked loop (DLL) of a dynamic random access memory (DRAM) is provided herein. A phase detector of the DLL compares an external clock signal with a feedback clock signal to generate a first control signal. A delay line circuit of the DLL delays the external clock signal according to the first control signal. A detector of the DRAM detects variations of the first control signal to determine a length of an enable period of an enable signal. The delay line circuit and the output buffer are active only during the enable period when the DRAM is in a standby mode. | 01-31-2013 |
20150078112 | METHOD FOR AUTO-REFRESHING MEMORY CELLS IN SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY DEVICE USING THE METHOD - An exemplary embodiment of the present disclosure illustrates a method for auto-refreshing memory cells in a semiconductor memory device with an open bit line architecture, wherein the semiconductor memory device comprises M memory banks, and each of the M memory banks has two particular sectors with a same index and L remained sectors with different indices. Two word lines of the two particular sectors with the same index in the memory bank and (M−1) word lines of the L remained sectors respectively in the other (M−1) memory banks are selected in one cycle. Then, memory cells of the selected word lines are refreshed. | 03-19-2015 |
Patent application number | Description | Published |
20080236793 | WATER BLOCK - A water block is used to be adhered to a heat-generating element and includes a cavity. The cavity has a chamber therein. One side or both sides of the chamber is provided with an inlet pipeline and an outlet pipeline respectively, thereby communicating with the chamber. Further, the chamber is provided therein with a heat-exchanging means for performing a heat-exchanging action with a working fluid. Finally, the top face of the cavity is provided with a membrane. An activating element is adhered on the membrane for driving the membrane to swing up and down, thereby forcing the working fluid within the chamber to circulate in single direction. The activating element is used as a power source, and in addition, the water block can be made much thinner. | 10-02-2008 |
20080260552 | MEMBRANE PUMP - A membrane pump powered by an activating element includes a chamber body. The interior of the chamber body is provided with a first chamber and a second chamber that are in fluid communication with each other. One side or both sides of the chamber body are provided with an inlet pipeline and an outlet pipeline that are in fluid communication with the first chamber and second chamber, respectively. Valves are provided on the inner wall face of same side of the first chamber and the second chamber, thereby preventing the working fluid from generating a backflow phenomenon. Furthermore, the top surface of the chamber body is provided with a membrane. An activating element abuts on the membrane for driving the membrane to swing up and down, thereby pressing the working fluid within the first chamber to circulatively flow in one direction. Via this arrangement, in addition to miniaturize the pump structure to a further extent, the working performance of the pump and the flowing amount of the working fluid are also increased. | 10-23-2008 |
20080260553 | MEMBRANE PUMP DEVICE - A membrane pump device powered by an activating element includes a chamber body and a second chamber body. The interior of the chamber body is provided with a chamber. Both sides of the chamber body are provided with an inlet pipeline and an outlet pipeline that are in fluid communication with the aforementioned chamber, respectively. A valve is provided on the inner wall face of the chamber, thereby preventing the working fluid from generating a backflow phenomenon. Furthermore, the top surface of the chamber body is provided with a membrane. An activating element abuts on the membrane for driving the membrane to swing up and down, thereby pressing the working fluid within the chamber to circulatively flow in one direction. Finally, the second chamber body is in fluid communication with the chamber body. The interior of the second chamber body is provided with another valve. Via this arrangement, in addition to miniaturize the pump structure to a further extent, the working performance of the pump and the flowing amount of the working fluid are also increased. | 10-23-2008 |
20080283224 | WATER-COOLING HEAT-DISSIPATING SYSTEM - A water-cooling heat-dissipating system for facilitating a heat-dissipating action with a heat-generating element includes a water block and a heat exchanger. The above-mentioned components are in fluid communication with one another via a plurality of conduits. The water block is attached on the heat-generating element to absorb the heat generated by the heat-generating element. The top surface of the water block is provided with a membrane. The membrane is provided thereon with an activating element, so that the membrane swings up and down at one side thereof to guide the flow of the working fluid. The heat exchanger performs a heat-conducting action with the flowing working fluid, thereby dissipating the heat absorbed by the working fluid to the outside. In this way, the heat-generating element can be kept in a normal range of working temperature. | 11-20-2008 |
20080283225 | WATER-COOLING HEAT-DISSIPATING SYSTEM - A water-cooling heat-dissipating system for facilitating a heat-dissipating action with a heat-generating element includes a water block, a membrane pump, a water tank and a heat exchanger. The above-mentioned components are in fluid communication with one another via a plurality of conduits. The water block is attached on the heat-generating element to absorb the heat generated by the heat-generating element. The membrane pump generates a thrust to facilitate the working fluid to perform a cooling action. The water tank is used to store additional working fluid. The heat exchanger performs a heat-conducting action with the flowing working fluid, thereby dissipating the heat absorbed by the working fluid to the outside. In this way, the heat-generating element can be kept in a normal range of working temperature. | 11-20-2008 |
Patent application number | Description | Published |
20130222071 | Oscillator based on a 6T SRAM for measuring the Bias Temperature Instability - The present invention provides an oscillator which is based on a 6T SRAM for measuring the Bias Temperature Instability. The oscillator includes a first control unit, a first inverter, a second control unit, and a second inverter. The first control unit is coupled with the first inverter. The second control unit is coupled with the second inverter. The first control unit and the second control unit is used to control the first inverter and the second inverter being selected, biased, and connected respectively, so that the NBTI and the PBTI of the SRAM can be measured separately, and the real time stability of the SRAM can be monitored immediately. | 08-29-2013 |
20130223136 | SRAM based on 6 transistor structure including a first inverter, a second inverter, a first pass-gate transistor, and a second pass-gate transistor - The present invention provides a 6T SRAM including a first inverter, a second inverter, a first pass-gate transistor, and a second pass-gate transistor. The first inverter zs a first pull-up transistor and a first pull-down transistor. The second inverter includes a second pull-up transistor and a second pull-down transistor. The gate of the second pull-up transistor is coupled with the gate of the second pull-down transistor, and the drain of the second pull-up transistor is coupled with the drain of the second pull-down transistor. The SRAM can measure the trip voltage, the read disturb voltage, and the write margin by controlling the first bit line, the second bit line, the GND, the first word line, and the voltage source without changing of the physic parameter of the SRAM. | 08-29-2013 |
20130301343 | THRESHOLD VOLTAGE MEASUREMENT DEVICE - A threshold voltage measurement device is disclosed. The device is coupled to a 6T SRAM. The SRAM comprises two inverters each coupled to a FET. Power terminals of one inverter are in a floating state; the drain and source of the FET coupled to the inverter are short-circuited. Two voltage selectors, a resistor, an amplifier and the SRAM are connected in a negative feedback way. Different bias voltages are applied to the SRAM for measuring threshold voltages of two FETs of the other inverter and the FET coupled to the other inverter. The present invention uses a single circuit to measure the threshold voltages of the three FETs without changing the physical structure of the SRAM. Thereby is accelerated the measurement and decreased the cost of the fabrication process and measurement instruments. | 11-14-2013 |
20140269141 | WORDLINE DOUBLER - A memory includes a clock generator for providing a first clock signal responsive to a second clock signal and a feedback signal. A feedback loop provides the feedback signal and includes a tracking wordline, a tracking bitline, a tracking bit cell, and a tracking wordline driver for driving the tracking wordline responsive to the first clock signal. The memory includes a tracking wordline level tuner for reducing a voltage level of a tracking wordline signal on the tracking wordline responsive to a weak bit control signal. | 09-18-2014 |
20150109852 | DATA-CONTROLLED AUXILIARY BRANCHES FOR SRAM CELL - A circuit includes a first inverter, a second inverter, a first auxiliary branch and a second auxiliary branch. The first and second inverters are cross-coupled to form a first storage node and a second storage node. The first auxiliary branch is coupled to the first storage node and configured to assist the first inverter in holding data based on data stored at the second storage node during a read operation, and assist the first inverter in flipping data based on data to be written to the first storage node during a write operation. The second auxiliary branch is coupled to the second storage node and configured to assist the second inverter in holding data based on data stored in the first storage node during the read operation, and assist the second inverter in flipping data based on data to be written to the second storage node during the write operation. | 04-23-2015 |
Patent application number | Description | Published |
20140139373 | MULTIPATH SWITCHING SYSTEM HAVING ADJUSTABLE PHASE SHIFT ARRAY - A multipath switching system comprising of an adjustable phase shift array includes, an adjustable phase shift array module and a control module. The adjustable phase shift array module receives a radio-frequency (RF) signal, and includes at least one RF switch, at least one coupler and at least one phase shifter. The at least one RF switch, the at least one coupler and the at least one phase shifter form a number of transmission paths. The transmission paths respectively produce the processed transmission RF signals corresponding to different phase shifts to an antenna array. The control module controls the at least one RF switch and the at least one phase shifter of the adjustable phase shift array module, so that the antenna array radiates a wireless signal whose direction is corresponding to a predetermined angle in space polar coordinates. | 05-22-2014 |
20140140705 | METHOD AND APPARATUS FOR INTERFERENCE SUPPRESSION IN RADIO-OVER-FIBER COMMUNICATION SYSTEMS - According to one embodiment of a method for interference suppression in radio-over-fiber communication systems, the method uses a mode selection module to continuously update real time information of at least two mobile stations and determine to enter a cross mode or a single mode. In the single mode, when a mobile station approaches a switching point, a single mode command is issued to control at least one first specific remote antenna unit (RAU). In the cross mode, when an immediate cross condition is a new cross condition, a new cross mode table is generated, and when the position of any one mobile station of the at least two mobile stations cross a threshold, a cross mode command is issued to control at least one second specific RAU according to a corresponding cross mode table. | 05-22-2014 |