Patent application number | Description | Published |
20080238514 | LEVEL-CONVERTED AND CLOCK-GATED LATCH AND SEQUENTIAL LOGIC CIRCUIT HAVING THE SAME - A level-converted and clock-gated latch includes a pulse generator, a level converting unit, and a latch circuit. The pulse generator is provided with a first power-supply voltage and generates a pulse signal having a first voltage level, in response to a clock signal. The level converting unit is provided with a second power-supply voltage and generates an intermediate clock signal having a second voltage level, in response to an inverted clock signal, the clock signal and an enable signal. The latch circuit is provided with the second power-supply voltage, latches the intermediate clock signal, and provides a gated clock signal having the second voltage level. An activation interval of the gated clock signal is controlled based on the enable signal. | 10-02-2008 |
20090039936 | Flip-flop circuit, pipeline circuit including a flip-flop circuit, and method of operating a flip-flop circuit - Example embodiments relate to an electronic circuit, for example, a flip-flop circuit, a pipeline circuit including the flip-flop circuit and a method for operating the flip-flop circuit. A flip-flop circuit may include a precharge transistor configured to precharge an internal node to a first power supply voltage in response to a clock signal, a first pull-down unit configured to pull down a voltage of the internal node to a second power supply voltage, a pull-up transistor configured to pull up a voltage of an output node to the first power supply voltage in response to the voltage of the internal node, and a second pull-down unit configured to pull down the voltage of the output node to the second power supply voltage. The pipeline circuit may include a pulse generating circuit, a first flip-flop group, a combination logic circuit, and a second flip-flop group. A method for operating a flip-flop circuit may include precharging an internal node to a first power supply voltage in response to a clock signal, pulling down a voltage of the internal node, pulling down the voltage to a second power supply voltage in response to a first pulse signal, and pulling up a voltage of an output node to the first power supply voltage. | 02-12-2009 |
20090201069 | LEVEL SHIFTING CIRCUIT - A level shifting circuit includes a first level shifting unit including a plurality of signal transfer units; a first operation control unit inactivating some of signal transfer units of the first level shifting unit in response to a clamping signal; a second level shifting unit connected in parallel to the first level shifting unit and comprising a plurality of signal transfer units; a second operation control unit inactivating some of signal transfer units of the second level shifting unit in response to the clamping signal; a signal output unit connected to output ends of the first and second level shifting units; and a clamping unit fixing the output ends of the first and second level shifting units to a predetermined voltage level in response to the clamping signal. | 08-13-2009 |
20090212838 | Delay Circuit Having Long Delay Time and Semiconductor Device Comprising the Same - A delay circuit has a long delay time and a semiconductor device includes the delay circuit. The delay circuit includes an inverter circuit unit having at least one inverter. Each of the inverters includes a first transistor connected to a supply voltage and a second transistor connected to a ground voltage. The inverter circuit unit receives a first signal and outputs a second signal by delaying the first signal. At least one capacitor unit is connected to an input terminal of the inverter such that a loading capacitance of the inverter circuit unit is increased. | 08-27-2009 |
20090237136 | Pulse-Based Flip-Flop Having Scan Input Signal - A flip-flop for transmitting a scan input and data for scan-testing a semiconductor circuit is provided. The flip-flop includes a first pulse signal generator which generates a first pulse signal in response to a scan enable signal and an inversed scan input signal. A second pulse signal generator generates a second pulse signal in response to the scan enable signal and a scan input signal. A signal transmitter receives a data signal and transmits the data signal to a first node in response to either one of the first and second pulse signals. A signal latch unit receives the data signal transmitted to the first node, and latches and outputs the data signal in response to another one of the first and second pulse signals. | 09-24-2009 |
20090237137 | Flip-Flop Capable of Operating at High-Speed - A flip-flop is provided for minimizing an input-output (D-Q) delay. The flip-flop includes a pull-up unit that receives a signal from a first node, is connected between a power voltage source and a second node, and pulls-up a voltage of the second node. A pull-down unit receives the signal from the first node, is connected between a ground voltage source and the second node, and pulls-down the voltage of the second node. A latch unit is connected to the second node and latches and outputs a signal transferred to the second node. The pull-up unit pulls-up the second node in response to one of a clock signal and a pulse signal, and the pull-down unit pulls-down the second node in response to the other one of the clock signal and the pulse signal. | 09-24-2009 |
20100073028 | Level-converting flip-flop and pulse generator for clustered voltage scaling - Provided is a level converting flip-flop for clustered voltage scaling and a level-converting pulse generator for use in the flip-flop. The flip-flop may include a pulse generator that receives an input clock signal with a high level equal to a first level and generates a pulse signal with a high level that may be converted into a second level higher than the first level. The flip-flop may further include a latch that latches input data with a high level equal to a third level lower than the second level and outputs output data with a high level that may be converted into the second level in response to the pulse signal. The third level may be equal to the first level. A supply voltage of the second level may be used as a supply voltage to the latch. Both the pulse generator and the flip-flop may have a level converting function without additional circuits, and therefore, the operating speeds of the pulse generator and the flip-flop may be increased without increasing the area and power consumption of the system. | 03-25-2010 |
20100082726 | METHOD AND APPRATUS FOR UPDATING AND PROVIDING PRESENCE INFORMATION BASED ON POSITION INFORMATION - A presence service providing system and method is disclosed that provides presence information regarding presentities to watchers. The presence system sets mapping information, which contains the presence information that matches position information corresponding to at least one presentity. When the position information is received via a positioning system, the presence system detects the presence information, which matches the received position information, from the set mapping information. The detected presence information is transmitted from the presence system to a watcher. The presence service providing system can provide a variety of presence information according to the location of the presentity, so that watchers can more specifically and clearly identify the states of the presentity from the presence information. | 04-01-2010 |
20100201344 | Method of Measuring Setup Time with Consideration of Characteristic of Absorbing Clock Skew in a Pulse-Based Flip-Flop - A method of measuring setup time measures a first delay time from an input signal to a clock signal and a second delay time from the clock signal to an output signal, and determines a setup time using the first delay time and the second delay time. The method of measuring setup time is used in designing a semiconductor IC including a pulse-based flip-flop circuit. The semiconductor IC designed by using the method of measuring setup time absorbs a clock jitter and allows a time borrowing between adjacent pipelines. | 08-12-2010 |
20100308864 | FLIP-FLOP CIRCUIT HAVING SCAN FUNCTION - A flip-flop circuit having a scan function includes an internal clock generator to receive a clock signal, a scan enable signal, and a first input signal, and to output an internal timing signal based on each of the clock signal, the scan enable signal, and the first input signal. The circuit includes a dynamic input unit to receive a second input signal, the scan enable signal, a first timing signal, and the internal timing signal, and to output a first output signal. The circuit also includes a static output unit to receive the first timing signal and the first output signal and to output a static output signal, and the dynamic input unit outputs the first output signal corresponding to one of the first input signal and the second input signal, respectively, based on a status of the scan enable signal. | 12-09-2010 |
20100315125 | DYNAMIC DOMINO CIRCUIT AND INTEGRATED CIRCUIT INCLUDING THE SAME - A dynamic domino circuit includes a clock generator and a domino circuit. The clock generator generates a pulse signal and a plurality of internal clock signals based on a global clock signal. Phases of the plurality of internal clock signals are sequentially delayed. The domino circuit sequentially performs a plurality of logic operations based on a plurality of input signals, the pulse signal and the plurality of internal clock signals and generates an output signal in synchronization with the pulse signal. The dynamic domino circuit may provide an effective interface with static logics. | 12-16-2010 |
20100315126 | DYNAMIC CIRCUIT WITH SLOW MUX INPUT - A logic circuit includes a control circuit including a first logic gate to receive a selection signal and a first input signal and to output a pulse control signal and a second logic gate to receive the pulse control signal, a clock signal, and a delayed clock signal and to output a pulse signal, and a multiplexing logic circuit to receive the selection signal and the pulse signal from the control circuit, to receive at least one second, static input signal, and to output a signal corresponding to one of the first input signal and the second, static input signal based on the state of the selection signal. | 12-16-2010 |
20100315144 | Flip-Flop Circuits and System Including the Same - Flip-flop circuits including a dynamic input unit and a control clock generator are provided. The dynamic input unit precharges an evaluation node to a power supply voltage in a first phase of a clock signal, selectively discharges the evaluation node based on input data in a second phase of the clock signal, and compensates for voltage drop of the evaluation node in response to a first control clock signal. The control clock generator generates the first control clock signal and a second control clock signal based on at least the clock signal. | 12-16-2010 |
20110165868 | METHOD AND APPARATUS FOR LOCATION BASED CALL SIGNAL CONVERSION SERVICE IN A WIRE-LESS COMMUNICATION NETWORK - The present invention relates to an apparatus and method for location based call signal conversion in a wireless communication network. The location based call signal conversion apparatus comprises an LBS (Location Based Service) server that provides location information on user terminals, and a call signal conversion server that converts the called signal to anyone called terminal on the called target terminal list that has been set up according to the current location of said called user terminal if a call connection request to a receiving user terminal from a sending user terminal is sensed among said user terminals, and if conditions for call signal conversion are satisfied according to the location and state of said called user terminal. | 07-07-2011 |
20110231723 | FLIP-FLOP CIRCUIT AND SCAN FLIP-FLOP CIRCUIT - A scan flip-flop circuit includes a pulse generator, a dynamic input unit and a latch output unit. The pulse generator generates a pulse signal which is enabled in synchronization with a rising edge of a clock signal in a normal mode, and is selectively enabled in synchronization with the rising edge of the clock signal in response to a logic level of a scan input signal in a scan mode. The dynamic input unit precharges a first node to a power supply voltage in a first phase of the clock signal, selectively discharges the first node in the normal mode, and discharges the first node in the scan mode. The latch output unit latches an internal signal provided from the first node to provide an output data, and determines whether the output data is toggled based on the clock signal and a previous state of the output data. | 09-22-2011 |
20120059903 | METHOD AND APPARATUS FOR PROCESSING SENSORY INFORMATION IN WIRELESS SENSOR NETWORK - A method and an apparatus for processing sensory information in a wireless sensor network are provided. The method includes determining at least one of sensor gateways as a serving sensor gateway to manage a target region in response to a sensory information request from a server, collecting the sensory information by means of at least one sensor node connected to the serving sensor gateway, and transmitting the collected sensory information to the server. | 03-08-2012 |
20120114068 | FLIP-FLOP INCLUDING KEEPER CIRCUIT - A flip-flop includes a transmission circuit configured to transmit data to a transmission line in response to a clock signal and a complementary clock signal. The flip-flop further includes a keeper circuit configured to latch data of the transmission line in response to the clock signal and the complementary clock signal to maintain the data of the transmission line constant. | 05-10-2012 |
20120134348 | APPARATUS AND METHOD FOR DETERMINING POSITION OF SENSOR NODE IN LOCATION SERVICE BASED SYSTEM - An apparatus and method for determining a position of a sensor node in a location service based system are provided. An operation method of a Secure User Plane Location (SUPL) Location Platform (SLP) for determining a position of a sensor node in a location service based system includes receiving a position determination request for a sensor node from an SUPL agent, interworking with a Location Registration Server (LRS) and acquiring routing information of the sensor node, sending a position determination start request for the sensor node to a gateway mapped to the sensor node using the acquired routing information, and interworking with the gateway and determining the position of the sensor node. | 05-31-2012 |
20120223739 | FLIP-FLOP AND SEMICONDUCTOR DEVICE INCLUDING THE SAME - A flip-flop is provided. The flip-flop includes a first latch circuit configured to latch a data signal in response to a plurality of first control signals or latch a scan input signal in response to a plurality of second control signals, and a second latch circuit configured to latch a signal output from the first latch circuit in response to complementary clock signals. | 09-06-2012 |
20120319753 | INTEGRATED CIRCUIT PULSE GENERATORS - An integrated circuit device includes a clock delay circuit configured to receive a clock signal and a pulse signal and to produce an output signal therefrom. The clock delay circuit is configured to transition the output signal to a first state responsive to a first state of the clock signal and to transition the output signal to a second state responsive to a first state transition of the pulse signal. The integrated circuit device further includes a pulse generator circuit configured to receive the clock signal and the output signal and to produce the pulse signal therefrom. The pulse generator circuit is configured to generate the first state transition in the pulse signal responsive to a transition of the clock signal to a second state and to generate a second state transition in the pulse signal responsive to the transition of the output signal to the second state. | 12-20-2012 |
20130241616 | Keeper Circuit And Electronic Device Having The Same - A keeper circuit includes a first latch and a second latch, each of the first latch and the second latch being configured to latch output data determined by input data during an evaluation phase, and the second latch, during a high-impedance phase, being configured to maintain output data of the second latch using output data of the first latch. | 09-19-2013 |
20130241617 | SCAN FLIP-FLOP, METHOD THEREOF AND DEVICES HAVING THE SAME - A scan flip-flop, which performs a normal operation latching a data input and a scan operation latching a scan input, includes a first circuit, a second circuit and a latch. The first circuit determines a voltage of an intermediate node based on a clock signal, one of the data input and the scan input, and data of a latch input node. The second circuit determines the data based on the clock signal, the voltage of the intermediate node and the data input during the normal operation, and determines the data based on the clock signal and the voltage of the intermediate node during the scan operation. The latch latches the data based on the clock signal. | 09-19-2013 |
20130246819 | FOOTER-LESS NP DOMINO LOGIC CIRCUIT AND RELATED APPARATUS - A domino logic circuit includes a pre-charge circuit pre-charging a first dynamic node in response to a clock signal, a first logic network determining a logic level of the first dynamic node in response to first data signals, an inverter receiving the clock signal, a discharge circuit discharging a second dynamic node in response to an output signal of the inverter, and a second logic network determining a logic level of the second dynamic node in response to at least one second data signal and an output signal of the first dynamic node. | 09-19-2013 |
20130257480 | CLOCK-DELAYED DOMINO LOGIC CIRCUIT AND DEVICES INCLUDING THE SAME - A clock-delayed domino logic circuit includes a precharge circuit configured to control connection between a first node and a dynamic node in response to a clock signal, an evaluation circuit configured to control connection between a second node and an evaluation node in response to the clock signal, a logic network connected between the dynamic node and the evaluation node, the logic network configured to determine a logic level of the dynamic node based on a plurality of input signals, and a phase control circuit configured to output a logic level of the evaluation node or a logic level of the first node according to a level of the clock signal. | 10-03-2013 |
20130275658 | FLASH MEMORY DEVICE AND METHOD OF PROGRAMMING THE SAME - A method is provided for programming a flash memory device including memory cells formed in a direction perpendicular to a substrate, a first sub word line connected to first memory cells and selectable by a first selection line, and a second sub word line connected to second memory cells and selectable by a second selection line, the first and second memory cells being formed at the same level and being supplied with a program voltage at the same time. The method includes performing LSB program operations on the first and second sub word lines by enabling the first and second selection lines, respectively; performing CSB program operations on the first and second sub word lines by enabling the first and second selection lines, respectively; and performing MSB program operations on the first and second sub word lines by enabling the first and second selection lines, respectively. | 10-17-2013 |
20140176212 | SCAN FLIP-FLOP, METHOD OF OPERATING THE SAME, AND DEVICE INCLUDING THE SCAN FLIP-FLOP - A scan flip-flop may include a selector outputting a data signal or a scan input signal in response to a scan enable signal, and a flip-flop that latches an output signal of the selector or the data signal, based on a clock signal and a low voltage signal. | 06-26-2014 |
20140184288 | SEMICONDUCTOR CIRCUIT AND METHOD FOR OPERATING THE SAME - Provided are a semiconductor circuit and method for operating the same. The semiconductor circuit includes a first flip-flop configured to, based on input data synchronized to a first clock, output first output data synchronized to a second clock different from the first clock, and a second flip-flop configured to, based on the first output data, output second output data synchronized to the second clock, wherein the first and the second flip-flops share an inverted second clock and a delayed second clock and output the first and the second output data based thereon, respectively. | 07-03-2014 |
20140247077 | SEMICONDUCTOR CIRCUIT - Provided is a semiconductor circuit. The semiconductor circuit includes a pulse generator which is enabled by a rising edge of a clock signal and generates a read pulse which varies depending on a voltage of a feedback node; and a sense amplifier which generates a voltage of a dynamic node and the voltage of the feedback node in accordance with a data value of an input signal using the read pulse. | 09-04-2014 |
20140266364 | SEMICONDUCTOR CIRCUIT AND METHOD OF OPERATING THE SAME - Provided are a semiconductor circuit and a method of operating the same. The semiconductor circuit includes a first pulse generating circuit enabled to a rising edge of a clock signal and configured to generate a first read pulse, a second pulse generating circuit enabled to a rising edge of the clock signal and configured to generate a second read pulse independent of the first read pulse, a dynamic pull-down stage configured to develop a voltage level of a first dynamic node based at least on data values of an input signal and the first and second read pulses, and a dynamic pull-up stage configured to develop a voltage level of a second dynamic node based at least on data values of the input signal and the first and second read pulses. | 09-18-2014 |
20140368246 | SEMICONDUCTOR DEVICE AND METHOD FOR OPERATING THE SAME - Provided are a semiconductor device and a method for operating a semiconductor device. The semiconductor device includes a clock generating unit receiving a reference clock and generating first and second clocks that are different from each other from the reference clock; a first latch configured to receive input data based on the first clock and to output the input data as first output data; and a second latch configured to receive the first output data based on the second clock and to output the first output data as second output data, wherein a first edge of the first clock does not overlap a first edge of the second clock, and at least a part of a second edge of the first clock overlaps a second edge of the second clock. | 12-18-2014 |
20150014775 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - Provided are a semiconductor device and a method of fabricating the semiconductor device. The semiconductor device includes a first source electrode configured to connect a first power rail to a first impurity region, the first power rail coupled to a first voltage source, a second source electrode configured to connect a second power rail to a second impurity region, the second power rail coupled to a second voltage source, the first and second voltage sources being different, a gate electrode on the first and second impurity regions, a first drain electrode on the first impurity region, a second drain electrode on the second impurity region and an interconnection line connected to the first drain electrode and the second drain electrode, the interconnection line forming at least one closed loop. | 01-15-2015 |
20150036447 | FLIP-FLOP WITH ZERO-DELAY BYPASS MUX - Exemplary embodiments may disclose a flip-flop circuit for inserting a zero-delay bypass mux including a master circuit which is configured to receive a data input, an input clock signal, and a bypass signal, and output an intermediate signal to a first node; and a slave circuit which is configured to receive the intermediate signal at the first node, the input clock signal, and the bypass signal, and output an output clock signal. The bypass signal controls the slave circuit to output one of a buffered input clock signal and a stretched clock signal as the output clock signal based on a logic level of the bypass signal. | 02-05-2015 |
20150048876 | SEMICONDUCTOR CIRCUIT - Provided is a semiconductor circuit. The semiconductor circuit includes: an input node configured to receive an enable signal, a sense enable signal, and a clock signal; and a clock gating circuit configured to output an enable clock signal corresponding to the clock signal while a signal level of the enable signal is at a first level regardless of a signal level of the sense enable signal, when the semiconductor circuit is in a high-voltage mode, and output an enable clock signal corresponding to the clock signal while a signal level of at least one of the enable signal and the sense enable signal is at the first level, when the semiconductor circuit is in a low-voltage mode. | 02-19-2015 |