Patent application number | Description | Published |
20080209248 | Method For Power Reduction And A Device Having Power Reduction Capabilities - A method for power reduction, the method includes determining whether to power down the at least portion of the component in response to a relationship between an estimated power gain and an estimated power loss resulting from powering down the at least portion of the component during the low power mode, and selectively providing power to at least a portion of a component of an integrated circuit during a low power mode. A device having power reduction capabilities, the device includes power switching circuitry adapted to selectively provide power to at least a portion of a component of the device during a low power mode, and a power management circuitry adapted to determine whether to power down at least the portion of the component during a low power mode in response to a relationship between an estimated power gain and an estimated power loss resulting from powering down the at least portion of the component during the low power. | 08-28-2008 |
20080256551 | System and Method For Storing State Information - A method for storing state information, the method includes storing, at a first circuit, state information representative of a state of a second circuit while the second circuit enters a low power mode; characterized by receiving an indication that a task switching from a first task to a second task should occur; storing a state information representative of a state of the second circuit, at the first circuit; receiving an indication that the first task should be resumed; and writing the stored state information from the first circuit to the second circuit. A system includes a first circuit and a second circuit, whereas the first circuit is connected to the second circuit and is adapted to store state information representative of a state of a second circuit; characterized by including a controller adapted to control a storage of the state information if at least a portion of the second circuit is powered down or if the second circuit is associated with a task switching operation. | 10-16-2008 |
20080265674 | System And Method For Controlling Voltage And Frequency In A Multiple Voltage Environment - A system that includes a first circuitry, a second circuitry, a first supply unit and a second supply unit; characterized by including a second control unit adapted to determine a level of a second supply voltage supplied by the second supply unit in response to an estimated power consumption of the second circuitry and an estimated power consumption of a voltage level shiftless interface circuitry that receives both the first and second supply voltages. A method for controlling voltage level and clock signal frequency supplied to a system, the method includes providing a first supply voltage to a first circuitry and providing a second supply voltage to a second circuitry; characterized by determining a level of the second supply voltage in response to an estimated power consumption of the second circuitry and an estimated power consumption of a voltage level shiftless interface circuitry that receives both the first and second supply voltages. | 10-30-2008 |
20080270858 | Device and Method for Configuring Input/Output Pads - A method for configuring IO pads, the method includes determining a current configuration of multiple IO pads of an integrated circuit and whereas the method is characterized by generating multiple boundary scan register words that comprise Configuration information; and repeating the stage of serially writing a certain boundary scan register word to a boundary scan register and outputting the boundary scan register word to multiple IO pad control circuits. A device that includes a core, connected to a boundary scan register, a TAP controller and multiple IO pad circuits, the device is characterized by including a control circuit adapted to determine a current configuration of the IO pads, to generate multiple boundary scan register words that comprise configuration information; and to control a repetition of: writing a certain boundary scan register word to the boundary scan register and outputting the boundary scan register word to multiple IO pad control circuits. | 10-30-2008 |
20080294927 | Method and System for Clock Skew Reduction in Clock Trees - A system that includes a clock tree and multiple variable delay components. The system is characterized by including a first set of fuses indicative of identities of variable delay components that belong to a first set of variable delay components, a second set of fuses indicative of delay values of the variable delay components that belong to the first set of variable delay components, and a second set of variable delay components that are set to at least one default delay value. A method for reducing clock skews, the method includes providing a clock tree that includes a set of variable delay components. The method is characterized by selecting a first set of variable delay components in view of timing violations occurring due clock skews, setting delay values of variable delay components that form a first set of variable delay components by programming fuses, and setting delay values of variable delay components that form a second set of variable delay components to at least one default value. | 11-27-2008 |
20080307133 | Method for Synchronizing a Transmission of Information and a Device Having Synchronizing Capabilities - A method for synchronizing a transmission of information over a bus, and a device having synchronization capabilities. The device includes: a bus that includes multiple bus lines, a bus transmitter connected between an information source and the bus, a bus receiver connected between the bus and an information target; wherein the information source and the information target are mutually asynchronous; wherein the device is characterized by including a bus receiver control circuit that controls the bus receiver circuit and a bus transmitter control circuit that controls the bus transmitter circuit; wherein the bus transmitter control circuit enables to transmit information from the information source to the bus in response to a change in a value of a feedback signal sent from the bus receiver control circuit and wherein the bus receiver control circuit enables to provide information from the bus to the information target in response to a change in a value of a delayed strobe signal provided by a delay unit connected between the bus receiver control circuit and the bus transmitter control circuit. | 12-11-2008 |
20090003114 | Apparatus and Method for Reducing Power Consumption Using Selective Power Gating - A method for reducing power consumption of transistor-based circuit, the method includes: of receiving a low power mode indication; determining whether to supply power to at least a portion of the transistor-based circuit in response to a reset value of the transistor-based circuit and a state of the transistor-based circuit prior the receiving of the low power mode indication, and selectively providing power to at least a portion of the transistor-based circuit. An apparatus for reducing power consumption of a transistor-based circuit, the apparatus being connected to the transistor-based circuit, and is adapted to receive a low power mode indication, wherein the apparatus includes: means for determining whether to supply power to at least a portion of the transistor-based circuit in response a state of the transistor-based circuit prior the receiving of the low power mode indication; and means for power gating, adapted to selectively provide power to at least a portion of the transistor-based circuit in response to the determination. | 01-01-2009 |
20090006013 | Device and a Method For Estimating Transistor Parameter Variations - A method and a device for estimating parameter variations of transistors that belong to the same circuit. The method includes: providing the first circuit; providing a test circuit adapted to perform a first function and a stacked test circuit adapted to perform a second function that substantially equals the first function; wherein the test circuit, the stacked test circuit and the first circuit are processed under substantially the same processing conditions; determining a relationship between a parameter of the test circuit and a parameter of the stacked test circuit; and estimating parameter variations of transistors that belong to the first circuit in response to the determined relationship. | 01-01-2009 |
20090015232 | METHOD AND DEVICE FOR REGULATING A VOLTAGE SUPPLY TO A SEMICONDUCTOR DEVICE - A device for regulating a voltage supply to a semiconductor device, the device comprising memory for storing a plurality of performance ranges, wherein the respective performance ranges are associated with a respective supply voltage; means for measuring the performance of the semiconductor device; and a regulator for modifying the supply voltage to the semiconductor device if the measured performance of the semiconductor device is not within a predetermined portion of the performance range associated with the voltage supplied to the semiconductor device. | 01-15-2009 |
20090027819 | DEVICE HAVING FAILURE RECOVERY CAPABILITIES AND A METHOD FOR FAILURE RECOVERY - A device that has failure recovery capabilities and a method for power recovery. The method includes: detecting a potential power failure in response to a decrement rate of a supply voltage, and applying at least one failure recovery measure in response to a detected potential power failure. The device includes: a power source, an energy reservoir, at least one component, and a power failure circuit, adapted to detect a potential power failure in response to a decrement rate of a supply voltage. | 01-29-2009 |
20090100276 | SYSTEM AND METHOD FOR CONTROLLING VOLTAGE LEVEL AND CLOCK FREQUENCY SUPPLIED TO A SYSTEM - A system that includes at least one component adapted to execute at least one application, characterized by including a controller adapted to receive at least one load indication of at least one component of the system and to selectively alter at least one control parameter of a voltage and clock frequency management scheme; whereas the system is adapted to apply the voltage and clock frequency management scheme. A method for controlling voltage level and clock frequency supplied to a system, the method includes receiving at least one load indication of at least one component of the system; characterized repeating the stages of: selectively altering at least one control parameter of a voltage and clock frequency management scheme; and applying the voltage and clock frequency management scheme. | 04-16-2009 |
20090129183 | METHOD AND DEVICE FOR HIGH SPEED TESTING OF AN INTEGRATED CIRCUIT - An integrated circuit and a method for testing an integrated circuit. The method includes providing a first high frequency clock signal sequence to a first group of components of an integrated circuit during a test sequence; characterized by receiving, by a first memory circuit within the integrated circuit, at a low reception rate, a first high frequency signal pattern information and a first low frequency signal pattern information; generating the first high frequency clock signal sequence in response to a first high frequency clock signal and in response to the first high frequency signal pattern information; wherein the first high frequency signal pattern information is being retrieved at a first high retrieval rate from the first memory circuit; and generating a first low frequency clock signal sequence in response a first low frequency clock signal and in response to the first low frequency signal pattern information; wherein the first high frequency signal pattern information is being retrieved at a low retrieval rate from the first memory circuit. | 05-21-2009 |
20090144572 | APPARATUS AND METHOD FOR CONTROLLING VOLTAGE AND FREQUENCY - A method and an apparatus for controlling voltage level and clock signal frequency supplied to a system. The apparatus includes a hardware module, adapted to receive at least one indication of a load of the system and to determine a voltage level and a clock signal frequency to be provided to the system, and a software module, adapted to configure a voltage source and a clock signal source in response to the determination. The method includes: (i) receiving, at a hardware module, indication of a load of a system; (ii) determining, by the hardware module, a voltage level and a clock signal frequency to be provided to the system; and (iii) configuring, by a software module, a voltage source and a clock signal source in response to the determination. | 06-04-2009 |
20090171646 | METHOD FOR ESTIMATING POWER CONSUMPTION - A method for determining system and software configuration that includes: calculating a power consumption estimate of a modeled system associated with an execution of a certain software code; and altering, in response to the power consumption estimate, the certain software code or the modeled system. A method of determining a power consumption of a system that executed a software code, the method includes the stages of: providing a reduced instruction set representation of the software code; and calculating a power consumption estimate of a modeled system associated with an execution of the reduced instruction set representation of the software code. | 07-02-2009 |
20090174452 | DEVICE AND METHOD FOR HANDLING METASTABLE SIGNALS - A method and device for managing metastable signals. The device includes: a first latch and a second latch, a multiple switching point circuit, connected between an output node of the first latch and an input node of the second latch, wherein the multiple switching point circuit includes at least one pull up transistor and at least one pull down transistor that are selectively activated in response to a feedback signal provided from the second latch and in response to a an output signal of the first latch such as to define at least a low switching point that is lower than a high switching point of the multiple-switching point circuit; wherein a switching point of an inverter within the first latch is between the high and low switching points. | 07-09-2009 |
20090177903 | METHOD AND DEVICE FOR POWER MANAGEMENT - A device and method for power management. The method includes receiving an indication about a load of a circuit, determining at least one long-term activation parameter in view of a circuit load pattern during at least one long period; determining at least one short-term activation parameter in response to an expected short period load change of the circuit; and providing least one clock signal and at least one supply voltage in response to the long-term activation parameter and in response to the short-term supply parameter. | 07-09-2009 |
20090195265 | DEVICE AND METHOD FOR TESTING INTEGRATED CIRCUITS - A method and device for testing an integrated circuit. The method includes selecting between a shadow latch data retention mode and a shadow latch test mode; performing first test of an integrated circuit; storing, at the shadow latch if the shadow latch test mode is selected, information representative of a first test-imposed state; performing a second test of the integrated circuit; and generating a test equipment detectable signal if the first test-imposed state differs from a second test-imposed state of the tested latch. | 08-06-2009 |
20090249142 | METHOD FOR RACE PREVENTION AND A DEVICE HAVING RACE PREVENTION CAPABILITIES - A method for race prevention and a device that has race prevention capabilities. The method includes: selectively providing data or scan data to a input latching logic, activating the input latching logic for a first scan mode activation period, introducing a substantial time shift between the first scan mode activation period and a second scan mode activation period, and activating a output latching logic, connected to the input latching logic for a second scan mode activation period. The device includes: an interface logic, a input latching logic, a output latching logic and a control logic. The interface logic is adapted to selectively provide data or scan data to the input latching logic. The control logic is adapted to introduce a substantial time difference between an end point of a first scan mode activation period of the input latching logic and between a start point of a second scan mode activation period of the output latching logic. | 10-01-2009 |
20090315601 | DEVICE AND METHOD FOR TIMING ERROR MANAGEMENT - A device having timing error management capabilities and a method for timing error management. The device includes a first input node adapted to receive input data; a first latch, a second latch and a comparator, rising a first multiplexer and a second multiplexer; wherein the second multiplexer is adapted to provide input data to the second latch from the first input mode during a first operational mode of the device and to provide a first latch output signal to the second latch during a second operational mode; wherein the comparator is adapted to compare, during a first clock phase, between the first latch output signal and between a second latch output signal and in response to the comparison selectively generate an error signal. | 12-24-2009 |
20090322367 | INTEGRATED CIRCUIT AND A METHOD FOR MEASURING A QUIESCENT CURRENT OF A MODULE - A method for evaluating a quiescent current, the method includes: measuring, when a module is at a first mode, a first voltage drop on a first resistor that is coupled between a supply pin of an integrated circuit that comprises the module and a first test pin of the integrated circuit; assessing, when the module is at a second mode, a second voltage drop on a second resistor that is coupled between the supply pin and a second test pin of the integrated circuit; and evaluating a quiescent current of the module in response to the first and second voltage drops; wherein expected values of quiescent current of the module differ from one mode to the other; and wherein a resistance of the first resistor differs from the resistance of the second resistor. | 12-31-2009 |
20090322385 | DEVICE HAVING CLOCK GENERATING CAPABILITIES AND A METHOD FOR GENERATING A CLOCK SIGNAL - A method for generating a clock signal and a device having clock generating capabilities, the device includes: (i) a first divider, adapted to receive an input clock signal and divide the input clock signal to provide a first clock signal; (ii) a second divider, adapted to receive an input clock signal and divide the input clock signal to provide a second clock signal; wherein the first clock signal is phase shifted in relation to the second clock signal by half an input clock cycle; wherein a delay period of the first divider substantially equals a delay period of the second divider over a large range of delay affecting parameter values; (iii) a reconstruction circuit, connected to the first and second divider circuits, adapted to receive the first and second clock signals and apply a logical operation on the first and second clock signals to provide a reconstructed clock signal; and (iv) a selection circuit, connected to the first divider, second divider and reconstruction circuit, adapted to output an output clock signal in response to a selection signal that indicates whether to output the first clock signal, the second clock signal or the reconstructed clock signal. | 12-31-2009 |
20090327795 | METHOD FOR PROTECTING A SECURED REAL TIME CLOCK MODULE AND A DEVICE HAVING PROTECTION CAPABILITIES - A method for protecting a secured real time clock module, the method includes: locking multiple input ports of the secured real time clock module if the multiple input ports of the secured real time clock module are idle during at least a first duration; unlocking the multiple input ports of the secured real time clock module if a predefined high frequency code is received over a control input port of the secured real time clock module; and providing a secured real time clock signal when the multiple input ports of the secured real time clock module are locked and when the multiple input ports of the secured real time clock module are unlocked; wherein changes in a supply voltage results in a supply voltage induced changes of an input signal provided to an input port of the secured real time clock module; wherein a maximal frequency of the supply voltage induced changes of the input signal is lower then the high frequency of the predefined high frequency code. | 12-31-2009 |
20100019818 | DEVICE AND METHOD FOR POWER MANAGEMENT - A device having power management capabilities and a method for power management, the method includes: providing a clock signal and a supply voltage to at least one component of a device; detecting a timing error; delaying by a fraction of a clock cycle and in response to the detected timing error, a clock signal provided to at least one of the components; and determining a clock signal frequency and a level of the supply voltage in response to at least one detected timing error. | 01-28-2010 |
20100019821 | METHOD FOR GENERATING A OUTPUT CLOCK SIGNAL HAVING A OUTPUT CYCLE AND A DEVICE HAVING A CLOCK SIGNAL GENERATING CAPABILITIES - A device and a method for generating a output clock signal having a output cycle, the method includes: (i) adjusting a delay of an adjustable ring oscillator to provide a high frequency clock signal having a short cycle so that the output cycle substantially equals a sum of integer multiples of a sleep cycle and integer multiplies of the short cycle; wherein the output cycle differs from any integer multiples of the sleep cycle; wherein the sleep cycle characterizes a sleep clock signal that is generated by a low frequency sleep clock; wherein the short cycle is shorter than the sleep cycle; (ii) counting short cycles and sleep cycles; and (iii) generating, during a sleep mode, in response to the counting and to a predefined counting pattern, the first clock signal; wherein the generating includes activating the adjustable ring oscillator only during a portion of a single sleep cycle per each output cycle. | 01-28-2010 |
20100019837 | SYSTEM AND METHOD FOR POWER MANAGEMENT - A system, that includes: a memory unit adapted to store state duration statistics indicative of possible low power state durations and probabilities associates with the possible state durations; and a power controller, adapted to: receive a request to cause a circuit to enter a next state, and assist in causing the circuit to enter the next state if during a delay period that follows a reception of the request the power controller does not receive a request to cause the circuit to exit the next state; wherein the delay period is determined in response to: (i) the next state duration statistics, (ii) power saving gained from entering the next state; and (iii) power penalty associated with entering the next state and exiting the next state. | 01-28-2010 |
20100023653 | SYSTEM AND METHOD FOR ARBITRATING BETWEEN MEMORY ACCESS REQUESTS - A system having memory access capabilities, the system includes: (i) a dynamic voltage and frequency scaling (DVFS) controller, adapted to determine a level of a voltage supply supplied to a first memory access requester and a frequency of a clock signal provided to the first memory access requester and to generate a DVFS indication that is indicative of the determination; (ii) a hardware access request determination module, adapted to determine a priority of memory access request issued by the first memory access requester in response to the DVFS indication; and (iii) a direct memory access arbitrator, adapted to arbitrate between memory access requests issued by the first memory access requester and another memory access requester in response to priorities associated with the memory access requests. | 01-28-2010 |
20100045363 | DEVICE AND METHOD FOR SHARING CHARGE | 02-25-2010 |
20100060342 | METHOD FOR POWER REDUCTION AND A DEVICE HAVING POWER REDUCTION CAPABILITIES - A device that includes: (i) an evaluated circuit; (ii) a leakage current dependent oscillator configured to generate an oscillating signal that has an oscillating frequency that represents a leakage current of the evaluated circuit; (iii) a switching current dependent oscillator configured to generate an oscillating signal that has an oscillating frequency that represents a switching induced current of the evaluated circuit; (iv) a power reduction module that is configured to: (a) compare between an oscillation frequency of the leakage current dependent oscillator and an oscillation frequency of the switching current dependent oscillator, to provide a current comparison result; (b) select a power reduction technique out of a dynamic voltage and frequency scaling technique and a power gating technique in view of the current comparison result; and (c) apply the selected power reduction technique. | 03-11-2010 |
20100070791 | POWER SUPPLY MONITORING METHOD AND SYSTEM - A device having a power supply monitoring capabilities, the device includes: a power supply unit; at least one real time clock generator counter adapted to receive a supply voltage from the power supply unit; a fixed value storage circuit that is un-accessible to software executed by a processor; wherein the fixed value storage circuit stores a fixed value; wherein the fixed value includes multiple bits; a volatile storage unit, being accessible to the processor; wherein the volatile storage unit is adapted to: (i) store a reset value after being reset; (ii) receive the fixed value during an initialization state; and (iii) store the fixed value until being reset; wherein the volatile storage unit is designed such that there is a low probability that the reset value equals the fixed value; and a comparator adapted to provide a tamper indication if the fixed value stored at the fixed value storage circuit differs from a value stored at the volatile storage unit. | 03-18-2010 |
20100182055 | DEVICE AND METHOD FOR DETECTING AND CORRECTING TIMING ERRORS - A device that includes an error detection circuit that is configured to detect a timing error resulting from a fast voltage drop by comparing a signal from a critical path to a signal from a replica path; and a clock signal provider that is adapted to receive a clock signal and to delay, by a fraction of the clock cycle and in response to a detection of the timing error, the clock signal to provide a delayed clock signal that is provided to a clocked circuit that is coupled to the critical path; and a controller that is configured determine a level of a supply voltage in response to a capability of the error detection circuit and the clock signal provider to manage fast voltage drops; wherein the supply voltage is provided to at least one component of the critical path. | 07-22-2010 |
20100185878 | METHOD FOR CONTROLLING POWER CONSUMPTION AND A DEVICE HAVING POWER CONSUMPTION CAPABILITIES - A method for controlling power consumption of a processor, the method includes: receiving an indicator that indicates that the processor is expected to change its activity; determining, in response to the indicator and to a current power consumption of the processor, whether to change a frequency of a clock signal that is provided to the processor; and changing, if determining to change the frequency of the clock signal, the frequency of the clock signal by a reduction of the frequency of the clock signal that is followed by an increment of the frequency of the clock signal; wherein the changing of the frequency of the clock signal is responsive to an expected change of a supply voltage that is supplied to the processor as a result of a possible change in a power consumption of the processor due to an expected change of activity of the processor. | 07-22-2010 |
20100202235 | DEVICE AND METHOD FOR STATE RETENTION POWER GATING - A device for state retention power gating, the device includes a group of circuits, each circuit is characterized by a reset state, wherein the device is characterized by including: a first memory entity adapted to save during a shut down period of the group circuits, at least one location of at least one non-reset-state circuit of the group of circuits. | 08-12-2010 |
20100225357 | REAL TIME CLOCK MONITORING METHOD AND SYSTEM - Method for monitoring a real time clock and a device having real time clock monitoring capabilities, the device includes: (i) a real time clock tree, (ii) a clock frequency monitor that is adapted to determine a frequency of a real time clock signal, during a short monitoring period; (iii) a monitoring enable module, adapted to activate the clock frequency monitor during short motoring periods and to deactivate the clock frequency monitor during other periods, wherein the monitoring enable module is adapted to determine a timing of the short monitoring periods in a non-deterministic manner; and (iv) a real time clock violation indication generator adapted to indicate that a real time clock violation occurred, in response to an error signal provided from the clock frequency monitor. | 09-09-2010 |
20100301907 | SYSTEM AND METHOD FOR SECURE REAL TIME CLOCKS - A secure real time clock (RTC) system is provided, comprising a secure RTC, a frequency signal generator, and a frequency adjuster connected between the secure RTC and the frequency signal generator to receive a signal having a first frequency from the frequency signal generator. On receipt of a first control signal the frequency adjuster outputs the signal having the first frequency to the secure RTC, and on receipt of a second control signal the frequency adjuster adjusts the signal having the first frequency to generate a signal having a second frequency, the second frequency being lower than the first frequency, and outputs the signal having the second frequency to the secure RTC. A clock line transmits the signal having the first frequency and the signal having the second frequency from the frequency adjuster to the secure RTC, and has a first power consumption when transmitting the signal having the first frequency and a second power consumption when transmitting the signal having the second frequency, the first power consumption being greater than the second power consumption. | 12-02-2010 |
20100332851 | METHOD FOR PROTECTING A CRYPTOGRAPHIC MODULE AND A DEVICE HAVING CRYPTOGRAPHIC MODULE PROTECTION CAPABILITIES - A device and a method for protecting a cryptographic module of which the method includes: estimating a functionality of a circuit that is adapted to malfunction when a physical parameter has a first value different from a nominal parameter value at which the cryptographic module functions correctly. The cryptographic module malfunctions when the physical parameter has a second value different from the nominal parameter value and a difference between the first value and the nominal parameter value being smaller than a difference between the second value and the nominal parameter value. A cryptographic module protective measure is applied if estimating that the circuit malfunctions. | 12-30-2010 |
20110018523 | DEVICE AND METHOD FOR CURRENT ESTIMATION - A device and a method for estimating a current; the method includes: setting an impedance of a power gating circuit to a measurement value; wherein the power gating circuit selectively provides power to a circuit of an integrated circuit; measuring, during a measurement period, an electrical parameter indicative of a current that flows through the power gating circuit; and reducing an impedance of the power gating circuit to a power provision value to reduce a voltage developed on the power gating circuit during a power provision period. | 01-27-2011 |
20110022869 | DEVICE HAVING MULTIPLE INSTRUCTION EXECUTION MODULES AND A MANAGEMENT METHOD - A multiple instruction execution modules device that comprises a first instruction execution module and a second instruction execution module and a context switch controller; wherein the first instruction execution module is logically identical to the second instruction execution module but substantially differs from the second instruction execution module by at least one power consumption characteristic; wherein the context switch controller controls a context switch between the first instruction execution module and the second instruction execution module; wherein an instruction execution module that its context has been transferred is shut down. | 01-27-2011 |
20110055648 | SYSTEM AND A METHOD FOR TESTING CONNECTIVITY BETWEEN A FIRST DEVICE AND A SECOND DEVICE - A device and a method for testing a connectivity between a first device and a second device, the method includes: writing, at a first frequency and in a serial manner, a first test word to a source boundary scan register; writing a content of the source boundary scan register, at a second frequency and in a parallel manner, to a target boundary scan register; wherein the second frequency is higher than the first frequency; reading the content of the target boundary scan register; wherein the source and target boundary scan registers are selected from a first boundary scan register of the first device and a second boundary scan register of the second device; and evaluating a connectivity between the first and second device in response to a relationship between the first test word and the content of the target boundary scan register. | 03-03-2011 |
20110156752 | METHOD AND APPARATUS FOR GATING A CLOCK SIGNAL - A semiconductor device comprising clock gating logic. The clock gating logic comprises clock freezing logic arranged to receive a selected clock signal and an enable signal. The clock freezing logic is further arranged to output a gated clock signal substantially corresponding to the selected clock signal when the enable signal comprises an inactive state, and to freeze the output gated clock signal when the enable signal comprises an active state. The clock gating logic further comprises polarity comparison logic arranged to compare polarities of an input clock signal and the gated clock signal and selector logic arranged to select from the input clock signal and an inverted input clock signal, based on a result of a comparison of the polarities of the input clock signal and the gated clock signal and to provide the selected clock signal to the clock freezing logic. The polarity comparison logic and the selector logic being further arranged such that, upon the enable signal transitioning from an active state to an inactive state, the selected clock signal provided to the clock freezing logic comprises a polarity substantially equivalent to that of the gated clock signal. | 06-30-2011 |
20110199159 | METHOD AND APPARATUS FOR GENERATING A CLOCK SIGNAL - An integrated circuit comprising oscillator circuitry is arranged to generate a clock signal for functional logic module of the integrated circuit. The oscillator circuitry comprises a plurality of propagation paths, and is arranged to apply a transition signal to inputs of the plurality of propagation paths, and to cause the output clock signal to transition based on a propagation of the transition signal through a determined set of the propagation paths. | 08-18-2011 |
20120032719 | ELECTRONIC CIRCUIT AND METHOD FOR OPERATING A MODULE IN A FUNCTIONAL MODE AND IN AN IDLE MODE - A method and an electronic circuit, the electronic circuit includes: a module that comprises multiple flip-flops and a control signal providing circuit; a power management circuit arranged to provide to the module a supply voltage of a functional level when the module is in a functional mode, and to provide to the module a supply voltage of an idle level when the module is in an idle mode; wherein the control signal providing circuit is arranged to provide to the multiple flip-flops, when the module is in the functional mode, a control signal that facilitates a state change of each of the multiple flip-flops; wherein the control signal providing circuit is arranged to provide to the multiple flip-flops, when the module is in the idle mode, a control signal that prevents a state change of each of the multiple flip-flops; wherein the each of the control signal providing circuit and a plurality of flip-flops of the multiple flip-flops comprises at least one hybrid circuit that comprises a low-threshold transistor that is coupled in parallel to at least one high-threshold transistor; wherein each hybrid circuit is arranged to maintain information or a control signal when provided with the supply voltage of the idle level; and wherein high-threshold transistors of each hybrid circuit are arranged to maintain information or a control signal when provided with a supply voltage of a level that is higher than the idle level. | 02-09-2012 |
20120105125 | ELECTRONIC CIRCUIT AND METHOD FOR OPERATING A CIRCUIT IN A STANDBY MODE AND IN AN OPERATIONAL MODE - A method and an electronic circuit, the electronic circuit includes: a first circuit; a leakage measurement circuit arranged to determine a leakage level of the first circuit when the first circuit is in a standby mode, and to determine an information maintenance level of a supply voltage in response to the leakage level; and a voltage supply circuit arranged to provide to the first circuit a supply voltage of a functional level when the first circuit is in a functional mode, and to provide to the first circuit a supply voltage of the information maintenance level when the first circuit is in the standby mode; wherein the first circuit is arranged to maintain information when provided with the supply voltage of the information maintenance level. | 05-03-2012 |
20120206183 | RESPONSE TO WEAROUT IN AN ELECTRONIC DEVICE - An electronic device comprises a first component susceptible to a wearout effect, operation of which first component depends on an operating parameter, and a second component having an on-state and an off-state. The electronic device further comprises a time estimator for updating an estimate of an accumulated time the second component was in the on-state; and a controller for controlling the operating parameter on the basis of the accumulated time estimate so as to respond to the expected wearout effect. The first component and the second component may be the same, or the first component may have an on-state correlated to the on-state of the second component. The operating parameter may, for example, be a level or amplitude or correction value of one of the following: a voltage applied at the first component, an electric current fed to the first component, and a power provided to the first component. A method of operating such an electronic device is also disclosed. | 08-16-2012 |
20120218033 | INTEGRATED CIRCUIT AND METHOD FOR REDUCTION OF SUPPLY VOLTAGE CHANGES - An integrated circuit and a method. The integrated circuit includes an internal component having an output for providing a driven input signal; an output driver, connected to the internal component, for converting said driven input signal in an output signal; an output pad for outputting said output signal to a component outside the integrated circuit; a power grid configured to supply a supply voltage to the output driver; a controllable current consuming component connected to the power grid, said connectable current consuming component being controllable to consume current in accordance with a supply voltage change reduction pattern; a change detector connected to the internal component and the controllable current consuming component, for detecting a change in said driven input signal prior to said change resulting in a change in said output signal and to control said current consuming component to consume current in response to said detecting. | 08-30-2012 |
20120235732 | INTEGRATED CIRCUIT COMPRISING REFERENCE VOLTAGE GENERATION CIRCUITRY AND ELECTRONIC DEVICE - An integrated circuit comprises reference voltage generation circuitry for providing a reference voltage for use within a transmission of electrical signals. The reference voltage generation circuitry comprises a reference voltage node operably coupled via a plurality of resistance elements to a plurality of signal nodes such that the reference voltage node assumes as the reference voltage an average of the voltage values of the signal nodes to which it is coupled. | 09-20-2012 |
20120236630 | BYPASS CAPACITOR CIRCUIT AND METHOD OF PROVIDING A BYPASS CAPACITANCE FOR AN INTEGRATED CIRCUIT DIE - A bypass capacitor circuit for an integrated circuit (IC) comprises one or more capacitive devices, each arranged in a segment of a seal ring area of a die, which comprises the IC. A method of providing a bypass capacitance for an IC comprises providing a semiconductor wafer device comprising a plurality of dies, each comprising an IC; arranging one or more capacitive devices in a seal ring area of at least one of the IC; dicing the semiconductor wafer device; in a test mode, for each of the one or more capacitive devices, enabling the capacitive device, determining an operability parameter value indicative of an operability of the capacitive device, and storing the operability parameter in a memory device; and in a normal operation mode, providing a bypass capacitance to the IC depending on a capacitance of one or more of the capacitive devices having an associated operability parameter value indicative of a non-defectiveness of the corresponding capacitive device. | 09-20-2012 |
20120239960 | METHOD FOR COMPENSATING A TIMING SIGNAL, AN INTEGRATED CIRCUIT AND ELECTRONIC DEVICE - A method for compensating a timing signal with which an outputting of data states of at least one data signal is synchronised. The method comprises receiving a current set of data states and a next set of data states, identifying state transitions between the current set of data states and the next set of data states, determining an amount of compensation to apply to the timing signal based at least partly on the state transitions identified between the current set of data states and the next set of data states, and applying the determined amount of compensation to the timing signal such that the compensation applies to the outputting of the next set of data states. | 09-20-2012 |
20120319731 | INTEGRATED CIRCUIT DEVICE COMPRISING CLOCK GATING CIRCUITRY, ELECTRONIC DEVICE AND METHOD FOR DYNAMICALLY CONFIGURING CLOCK GATING - An integrated circuit comprises clock gating circuitry comprising at least one gating component located within a clock distribution network and arranged to enable at least one part of the clock distribution network to be gated, and gating control circuitry arranged to cause the at least one gating component to disable the at least one part of the clock distribution network upon certain conditions being fulfilled. The clock gating circuitry further comprises clock gating disabling circuitry configurable to enable the gating of the at least one part of the clock distribution network to be disabled. | 12-20-2012 |
20130002334 | INTEGRATED CIRCUIT, ELECTRONIC DEVICE AND METHOD FOR CONFIGURING A SIGNAL PATH FOR A TIMING SENSITIVE SIGNAL - An integrated circuit comprising at least one signal path for a timing sensitive signal. At least one section of the signal path comprises a first section path comprising a first propagation timing factor, at least one further section path comprising a second propagation timing factor different to the first propagation timing factor, and a path selection component arranged to enable the selection of one of the first and at least one further section paths via which the timing sensitive signal is to propagate through the at least one section of the signal path based on at least one from a group consisting of: the first propagation timing factor, second propagation timing factor. | 01-03-2013 |
20130007431 | INTEGRATED CIRCUIT DEVICE, SIGNAL PROCESSING SYSTEM, ELECTRONIC DEVICE AND METHOD THEREFOR - An integrated circuit device comprises a signal processing system having at least one first signal processing module fabricated by way of a first production process; and at least one second signal processing module fabricated by way of a second production process, wherein the second production process is different to the first production process. The signal processing system further comprises a signal processing management module arranged to: determine a desired system performance of the integrated circuit device; determine at least one operating condition of the signal processing system; and configure a signal processing operating mode of the signal processing system based at least partly on: the determined desired system performance; the at least one determined operating condition; and at least one of the first production process and the second production process. | 01-03-2013 |
20130015904 | POWER GATING CONTROL MODULE, INTEGRATED CIRCUIT DEVICE, SIGNAL PROCESSING SYSTEM, ELECTRONIC DEVICE, AND METHOD THEREFORAANM Priel; MichaelAACI HertzeliaAACO ILAAGP Priel; Michael Hertzelia ILAANM Rozen; AntonAACI GederaAACO ILAAGP Rozen; Anton Gedera ILAANM Shoshany; YossiAACI Gan YavneAACO ILAAGP Shoshany; Yossi Gan Yavne IL - An integrated circuit device comprising at least one signal processing module and a power gating control module arranged to control gating of at least one power supply to at least a part of the at least one signal processing module. The power gating control module is arranged to receive at least one operating parameter; configure at least one power gating setting of the power gating control module based at least partly on the at least one received operating parameter; and apply power gating for at least part of the at least one signal processing module in accordance with the at least one configured power gating setting. | 01-17-2013 |
20130027082 | VOLTAGE LEVEL SHIFTER, DECOUPLER FOR A VOLTAGE LEVEL SHIFTER, AND VOLTAGE SHIFTING METHOD - A voltage level shifter for translating a binary input signal representing a binary sequence to a binary output signal representing the same binary sequence. The voltage level shifter comprises an input port for receiving the binary input signal as an input voltage varying between a first input voltage level and a second input voltage level. An output port is connected to a node for outputting the binary output signal as an output voltage varying between a first output voltage level and a second output voltage level. A supply voltage node connectable to a voltage supply, can provide the second output voltage level. A first switch is arranged to couple the supply voltage node to the node and to decouple the supply voltage node from the node based on a voltage at the node. A feedback voltage loop is connected to the node for providing a feedback voltage based on the voltage at the node. A second switch is connected to the feedback voltage loop and arranged to couple the input port to the node based on a voltage at the input port and the feedback voltage. A decoupler and a voltage shifting method are also disclosed. | 01-31-2013 |
20130027109 | VOLTAGE LEVEL SHIFTER HAVING A FIRST OPERATING MODE AND A SECOND OPERATING MODE - Embodiments of the present invention provide a voltage level shifter used to translate a binary input signal representing a binary sequence to a binary output signal representing the same binary sequence. The input signal is provided by an input voltage varying between a first input voltage level and a second input voltage level. The output signal is provided by an output voltage varying between a first output voltage level and a second output voltage level. The output signal has a delay relative to the input signal, and the voltage level shifter has a leakage current. The voltage level shifter has a first operating mode and a second operating mode. In the second operating mode, the delay is shorter while the leakage current is higher than in the first operating mode. | 01-31-2013 |
20130076421 | ELECTRONIC CIRCUIT AND METHOD FOR STATE RETENTION POWER GATING - A method and a electronic circuit, the method includes: sending to a switching circuit, to a state retention power gating (SRPG) circuit and to a first power source a control signal indicating that the SRPG circuit should operate in a functional mode; coupling, by the switching circuit, a third power grid to a first power grid; supplying power from the first power source to the SRPG circuit via the first power grid, the switching circuit and the third power grid; supplying power from a second power source to a second circuit via a second power grid; sending to the switching circuit, to the SRPG circuit and to the first power source a control signal indicating that the SRPG circuit should operate in a state retention mode; coupling, by the switching circuit, the third power grid to the second power grid; supplying power from the second power source to the SRPG circuit via the second power grid, the switching circuit and the third power grid; supplying power from the second power source to the second circuit via the second power grid; and storing, by the SRPG state information. | 03-28-2013 |
20130097449 | MEMORY UNIT, INFORMATION PROCESSING DEVICE, AND METHOD - A memory unit comprises at least two volatile memory elements, analyzing circuitry and power gate. The memory elements may for example be latches, flip-flops, or registers. Each of the memory elements has at least two different states including a predefined reset state. The analyzing circuitry generates a power-down enable signal in response to each of the memory elements being in its reset state. The power gate powers down the memory elements in response to the power-down enable signal. The memory elements may be arranged to assume their reset states upon powering up the memory unit. | 04-18-2013 |
20130124800 | APPARATUS AND METHOD FOR REDUCING PROCESSOR LATENCY - There is provided a data processing system comprising a central processing unit, a processor cache memory operably coupled to the central processing unit and an external connection operably coupled to the central processing unit and processor cache memory in which a portion of the data processing system is arranged to load data directly from the external connection into the processor cache memory and modify a source address of said directly loaded data. There is also provided a method of improving latency in a data processing system having a central processing unit operably coupled to a processor cache memory and an external connection operably coupled to the central processing unit and processor cache memory, comprising loading data directly from the external connection into the processor cache memory and modifying a source address for said data to become indicative of a location other than from the external connection. | 05-16-2013 |
20130124890 | MULTI-CORE PROCESSOR AND METHOD OF POWER MANAGEMENT OF A MULTI-CORE PROCESSOR - A multi-core processor includes a plurality of power gating elements for controlling power applied to each core. Each power gating element is coupled to a respective power gating controllers for controlling the respective power gating element to selectively provide full power to the respective core only during an active period of the respective core. A common power gating controller is coupled to the individual power gating controllers for controlling the individual power gating controllers to balance the active periods of the plurality of cores so as to substantially reduce or minimise overlapping active periods so as to reduce the total power provided to all the cores. | 05-16-2013 |
20130125077 | METHOD FOR OPTIMISING CELL VARIANT SELECTION WITHIN A DESIGN PROCESS FOR AN INTEGRATED CIRCUIT DEVICE - A method is provided for optimising cell variant selection within a design process for an integrated circuit device. The method comprises performing cell placement and signal routing for an integrated circuit being designed using default cell layout information for cell variants of at least one cell type. The method further comprises performing cell variant optimisation comprising identifying at least one cell of the at least one cell type to be substituted and substituting a default cell variant of the at least one identified cell with an alternative variant of the at least one identified cell. The method further comprises, during cell optimisation, configuring a pin interconnect modification for mapping at least one pin location of the alternative variant of the at least one identified cell to at least one pin contact for the default cell layout. | 05-16-2013 |
20130132753 | INFORMATION PROCESSING DEVICE AND METHOD - An information processing device comprises a first memory, a second memory, data transfer circuitry, power gating circuitry, and a controller. The first memory comprises at least two volatile memory units The controller receives or generates a request for setting the information processing device into a reduced power mode; in response to the request, it selects specific memory units among the memory units; controls the data transfer circuitry to transfer data from the selected memory units to the second memory; and controls the power gating circuitry to power down the selected memory units. | 05-23-2013 |
20130132756 | ELECTRONIC CIRCUIT AND METHOD FOR STATE RETENTION POWER GATING - An electronic circuit includes a processor having a functional mode and a low power mode, said processor comprising state flip-flops and additional flip-flops; said state flip flips are arranged to store state information about a state of the processor when the processor is in the functional mode; said state flip-flops comprise non-reset flip-flops that are arranged to store at least one non-reset value when the processor exits the functional mode; a power management circuit for providing power to the processor when the processor is in the functional mode, and for preventing power from the processor when the processor is in the low power mode; a non-reset value identification module, coupled to the state flip-flops, said non-reset value identification module is arranged to identify the non-reset flip-flops and to generate non-reset information that identifies the non-reset flip-flops; and a recovery circuit, coupled to a memory module and to the state flip-flops. | 05-23-2013 |
20130238912 | METHOD AND APPARATUS FOR MANAGING POWER IN A MULTI-CORE PROCESSOR - There is provided a method of managing power in a multi-core data processing system having two or more processing cores, comprising determining usage characteristics for the two or more processing cores within the multi-core processing unit, and dependent on the determined usage characteristics, adapting a frequency or voltage supplied to each of the two or more processing cores, and/or adapting enablement signals provided to each of the two or more processing cores. There is also provided an apparatus for carrying out the disclosed method. | 09-12-2013 |
20130241606 | INTEGRATED CIRCUIT AND A METHOD OF POWER MANAGEMENT OF AN INTEGRATED CIRCUIT - An integrated circuit includes a plurality of power gating elements for controlling power applied to a first module which is in a powered off state, while a second module is in a powered on state, the second module being coupled to receive at least one signal from the first module when the first module is powered on. A a synchronization controller is provided for controlling the power gating elements to ramp up the power gated to the first module in order to power it up and, for a time while the power gated to the first module is below a first level, reducing the power gated to the second module, and for a time when the power gated to the first module is above the first level, increasing the power gated to the second module. | 09-19-2013 |