Patent application number | Description | Published |
20080244346 | Circuit for Compression and Storage of Circuit Diagnosis Data - A compactor includes test data inputs that are connectable to circuit outputs of an electrical circuit, test comparison inputs, and test data outputs. The compactor further includes a number of H matrix XOR gates arranged as a switching mechanism between the test data inputs and the test data outputs such that data applied to the test data inputs is produced at the test data outputs compressed in accordance with coefficients of an H matrix of an error-correcting code, and compensation XOR gates arranged between the test data inputs and the test data outputs, each compensation XOR gate including an input for receiving a compensation value. | 10-02-2008 |
20080263421 | Electrical Diagnostic Circuit and Method for the Testing and/or the Diagnostic Analysis of an Integrated Circuit - An electrical diagnostic circuit and testing method is disclosed. In one embodiment the electrical diagnostic circuit for testing an integrated circuit includes a number of external inputs, a plurality of essentially similar, series-connected switching units and a circuit output. The switching units are constructed to be controllable in such a manner that an input signal present at the internal input of the switching unit, in dependence on a control signal of the switching unit, can either be forwarded unchanged to the internal input of the switching unit in each case arranged downstream, or can be combined with the test signal in each case present at the external input. | 10-23-2008 |
20090049369 | Circuit Arrangement and Method for Error Detection and Arrangement for Monitoring of a Digital Circuit - A circuit arrangement is formed as follows. A combinational circuit has n binary inputs E | 02-19-2009 |
20100070811 | CIRCUIT ARRANGEMENT - The invention relates to a circuit arrangement, comprising: a functional circuit with m (m=1, 2, . . . ) data inputs and n (n=1, 2, . . . ) data outputs for processing at least one m-dimensional binary data input (x | 03-18-2010 |
20110191658 | Method and Apparatus for Storing Data - When coding user data, it may be desirable to mark user data as invalid. This may arise, by way of example, in applications in which a stored data item needs to be updated by virtue of an updated data item additionally being stored and the old stored data item being marked as invalid. In order to mark the invalidity of a stored data item by means of the value of the data item and to be able to apply an error-recognizing or error-correcting coding dependably, the user data are extended by supplementary data and the coding is applied to the extended user data. | 08-04-2011 |
20120079343 | APPARATUS AND METHOD FOR DETERMINATION OF A POSITION OF A 1 BIT ERROR IN A CODED BIT SEQUENCE, APPARATUS AND METHOD FOR CORRECTION OF A 1-BIT ERROR IN A CODED BIT SEQUENCE AND DECODER AND METHOD FOR DECODING AN INCORRECT, CODED BIT SEQUENCE - An apparatus for determination of a position of a 1-bit error includes an error position determiner of the inner code, an error syndrome determiner of the outer code, a derivative determiner and an overall error position determiner. The error position determiner of the inner code determines at least one possible error position of a bit error in the coded bit sequence on the basis of the inner code. The error syndrome determiner of the outer code determines a value of a non-linear syndrome bit of the outer code on the basis of a non-linear function of bits in the coded bit sequence. Furthermore, the derivative determiner determines a value of a derivative bit for at least one determined, possible error position of the bit error on the basis of derivation of the non-linear function based on the bit at the determined, possible error position in the coded bit sequence. | 03-29-2012 |
20120117448 | Apparatus and Method for Correcting at least one Bit Error within a Coded Bit Sequence - An apparatus for correcting at least one bit error within a coded bit sequence includes an error syndrome generator and a bit error corrector. The error syndrome generator determines the error syndrome of a coded bit sequence derived by a multiplication of a check matrix with a coded bit sequence. | 05-10-2012 |
20130002288 | Electronic Circuit Arrangement for Processing Binary Input Values - Electronic circuit arrangement for processing binary input values xεX of a word width n (n>1), with a first, second and third combinatory circuit components configured to process the binary input values x to form first, second and third binary output values. The arrangement further includes a majority voter element configured to receive the binary output values and provide a majority signal based on the received binary output values. The second and third combinatory circuit components are designed, as regards faults during processing of the binary input values x in the first combinatory circuit component, to process binary input values of a true non-empty partial quantity X | 01-03-2013 |
20130173979 | HIGH PERFORMANCE COMPACTION FOR TEST RESPONSES WITH MANY UNKNOWNS - A circuit arrangement for controlling the masking of test and diagnosis data with X values of an electronic circuit with N scan paths, wherein the test data are provided on insertion into the N scan paths by a decompressor with m inputs and N outputs (m07-04-2013 | |
20130212441 | System and Method for Signature-Based Redundancy Comparison - A system and method for signature-based redundancy comparison provides for receiving, by a master part, an input signal and generating, by the master part, a binary output signal, generating a delayed input signal based on the input signal, generating a first output signature based on the binary output signal, and generating a delayed first output signature based on the first output signature. The system and method further comprise generating a delayed binary output signal based on the delayed input signal, generating, by a checker part, a delayed second output signature based on the delayed binary output signal, comparing the delayed first output signature with the delayed second output signature, and generating an error signal, where the state of the error signal is based upon the comparison. | 08-15-2013 |
20130212452 | Apparatus and Method for Comparing Pairs of Binary Words - An apparatus for comparing pairs of binary words includes an intermediate value determiner and an error detector. The intermediate value determiner determines an intermediate binary word so that the intermediate binary word is equal to a reference binary word for a first pair of equal or inverted binary words, so that the intermediate binary word is equal to the inverted reference binary word for a second pair of equal or inverted binary words and so that the intermediate binary word is unequal to the reference binary word and the inverted reference binary word for a pair of unequal and uninverted binary words, if the intermediate value determiner works faultlessly. Further, the error detector provides an error signal based on the intermediate binary word so that the error signal indicates whether or not the binary words of a pair of binary words are equal or inverted. | 08-15-2013 |
20130339819 | ERROR-TOLERANT MEMORIES - Methods and apparatuses relating to error-tolerant memories are provided. In one example embodiment, output signals from at least three memory devices are supplied to an error correction device. The error correction device outputs a corrected data value in such a manner that, when the read data values match, this data value is output and, in at least one state in which the data values do not match, a previously output data value is retained. | 12-19-2013 |
20130346834 | APPARATUS AND METHOD FOR CORRECTING AT LEAST ONE BIT ERROR WITHIN A CODED BIT SEQUENCE - An apparatus for correcting at least one bit error within a coded bit sequence includes an error syndrome generator and a bit error corrector. The error syndrome generator determines the error syndrome of a coded bit sequence derived by a multiplication of a check matrix with a coded bit sequence. | 12-26-2013 |
20140075272 | DEVICE AND METHOD FOR TESTING A CIRCUIT TO BE TESTED - A device for testing a circuit includes a syndrome determiner, a test sequence provider and an evaluation circuit. The syndrome determiner determines an error syndrome bit sequence (s(v′)) based on a coded binary word (v′). The error syndrome bit sequence (s(v′)) indicates whether the coded binary word (v′) is a code word of an error correction code (C) used for coding the coded binary word (v′). The test sequence provider provides a test bit sequence (T | 03-13-2014 |
20140122967 | Circuitry and Method for Multi-Bit Correction - A circuitry is provided that includes a memory including a plurality of memory cells, wherein at least one of the plurality of memory cells of the memory is configured to take on one of at least three different states. The circuitry also includes a first subcircuit BT configured to generate a plurality of ternary output values based on a sequence of binary values, a second subcircuit LH configured to transform one or more ternary state values into binary auxiliary read values based on the one or more state values, and an encoder configured to generate one or more binary check bits, wherein the encoder is configured to store each of the generated one or more check bits in a different memory cell. | 05-01-2014 |
20140173386 | Circuitry and Method for Correcting 3-bit Errors Containing Adjacent 2-Bit Error - A circuitry is proposed for the correction of errors in a possibly erroneous binary word v′=v′ | 06-19-2014 |
20150039952 | CIRCUIT ARRANGEMENT AND METHOD WITH MODIFIED ERROR SYNDROME FOR ERROR DETECTION OF PERMANENT ERRORS IN MEMORIES - A circuit arrangement for detecting memory errors is provided. The circuit arrangement comprises a memory ( | 02-05-2015 |
20150039976 | Efficient Error Correction of Multi-Bit Errors - A circuitry for error correction includes a plurality of subcircuits for determining intermediate values Zw | 02-05-2015 |
20150089333 | CIRCUIT ARRANGEMENT AND METHOD FOR REALIZING CHECK BIT COMPACTING FOR CROSS PARITY CODES - A circuit arrangement for determining m check bits c | 03-26-2015 |