# Micha Anholt, Tel Aviv IL

## Micha Anholt, Tel Aviv IL

Patent application number | Description | Published |
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20080240277 | Reducing computational complexity in maximum likelihood MIMO OFDM decoder - A method and a system for reducing computational complexity in a maximum-likelihood MIMO decoder, while maintaining its high performance. A factorization operation is applied on the channel Matrix H. The decomposition creates two matrixes: an upper triangular with only real-numbers on the diagonal and a unitary matrix. The decomposition simplifies the representation of the distance calculation needed for constellation points search. An exhaustive search for all the points in the constellation for two spatial streams t(1), t(2) is performed, searching all possible transmit points of (t2), wherein each point generates a SISO slicing problem in terms of transmit points of (t1); Then, decomposing x,y components of t(1), thus turning a two-dimensional problem into two one-dimensional problems. Finally searching the remaining points of t(1) and using Gray coding in the constellation points arrangement and the symmetry deriving from it to further reduce the number of constellation points that have to be searched. | 10-02-2008 |

20090106485 | READING ANALOG MEMORY CELLS USING BUILT-IN MULTI-THRESHOLD COMMANDS - A method for data storage includes storing data in a memory that includes multi-bit analog memory cells, each of which stores at least first and second data bits by assuming one of a predefined plurality of programming levels associated with respective storage values. The memory has at least a first built-in command for reading the first data bits of the memory cells by comparing the storage values of the memory cells to a first number of first thresholds, and a second built-in command for reading the second data bits of the memory cells by comparing the storage values of the memory cells to a second number of second thresholds, such that the first number is less than the second number. After storing the data, the first data bits are read from the memory cells by executing at least the second built-in command. | 04-23-2009 |

20090187803 | DECODING OF ERROR CORRECTION CODE USING PARTIAL BIT INVERSION - A method includes receiving an Error Correction Code (ECC) code word, which includes multiple encoded bits that represent data and have a bit order. Multiple subsets of the encoded bits are selected using a selection criterion that does not sequentially follow the bit order. For each subset in at least some of the multiple subsets, the bits in the subset are inverted and the code word having the inverted bits is decoded, so as to reconstruct the data. | 07-23-2009 |

20100091535 | ADAPTIVE ESTIMATION OF MEMORY CELL READ THRESHOLDS - A method for operating a memory ( | 04-15-2010 |

20100165689 | REJUVENATION OF ANALOG MEMORY CELLS - A method for data storage in a memory that includes multiple analog memory cells fabricated using respective physical media, includes identifying a group of the memory cells whose physical media have deteriorated over time below a given storage quality level. A rejuvenation process, which causes the physical media of the memory cells in the group to meet the given storage quality level, is applied to the identified group. Data is stored in the rejuvenated group of the memory cells. | 07-01-2010 |

20100332955 | CHIEN SEARCH USING MULTIPLE BASIS REPRESENTATION - A method for decoding an Error Correction Code (ECC) includes accepting coefficients, including at least first and second coefficients, of an Error Locator Polynomial (ELP) that is defined over a vector space and has at least one root that is indicative of a location of an error in a set of bits, which represent data that has been encoded with the ECC. The first coefficient is represented using a first basis of the vector space, and the second coefficient is represented using a second basis of the vector space, different from the first basis. Using processing circuitry, the root of the ELP is identified by applying algebraic operations to the coefficients, such that the algebraic operations are applied to the first coefficient using the first basis, and to the second coefficient using the second basis. The error is corrected responsively to the identified root of the ELP. | 12-30-2010 |

20120044762 | REJUVENATION OF ANALOG MEMORY CELLS - A method for data storage in a memory that includes multiple analog memory cells fabricated using respective physical media, includes identifying a group of the memory cells whose physical media have deteriorated over time below a given storage quality level. A rejuvenation process, which causes the physical media of the memory cells in the group to meet the given storage quality level, is applied to the identified group. Data is stored in the rejuvenated group of the memory cells. | 02-23-2012 |

20120221913 | ERROR CORRECTION CODES FOR INCREMENTAL REDUNDANCY - A method includes accepting input including at least part of a codeword that has been encoded by an ECC defined by a set of parity check equations. The codeword includes data bits and parity bits. A decoding process is applied to the codeword using the data bits and only a first partial subset of parity bits in the input, and using only a second partial subset of equations. Upon a failure to decode the codeword using the partial subsets, the codeword is re-decoded using the data bits and all parity bits in the input, and using all equations. The set of parity check equations is defined such that any parity bit in the codeword appears in multiple equations, and any parity bit in the first partial subset of the parity bits appears in a plurality of equations in the second partial subset of the equations. | 08-30-2012 |

20120246435 | STORAGE SYSTEM EXPORTING INTERNAL STORAGE RULES - A data storage method includes, in a memory controller that accepts memory access commands from a host for execution in one or more memory units, holding a definition of a policy to be applied by the memory controller in the execution of the memory access commands in the memory units. The policy is reported from the memory controller to the host so as to cause the host to format memory access commands based on the reported policy. | 09-27-2012 |

20120317457 | HIGH-PERFORMANCE ECC DECODER - Methods for Error Correction Code (ECC) decoding include producing syndromes from a set of bits, which represent data that has been encoded with the ECC. An Error Locator Polynomial (ELP) is generated based on the syndromes. At least some of the ELP roots are identified, and the errors indicated by these roots are corrected. Each syndrome may be produced by applying to the bits vector operations in a vector space. Each syndrome is produced by applying vector operations using a different basis of the vector space. The ELP may be evaluated on a given field element by operating on ELP coefficients using serial multipliers, wherein each serial multiplier performs a sequence of multiplication cycles and produces an interim result in each cycle. Responsively to detecting at least one interim result indicating that the given element is not an ELP root, the multiplication cycles are terminated before completion of the sequence. | 12-13-2012 |

20130073928 | POWER-OPTIMIZED DECODING OF LINEAR CODES - A method includes accepting an input code word, which was produced by encoding data with an Error Correction Code (ECC), for decoding by a hardware-implemented ECC decoder. The input code word is pre-processed to produce a pre-processed code word, such that a first number of bit transitions that occur in the hardware-implemented ECC decoder while decoding the pre-processed code word is smaller than a second number of the bit transitions that would occur in the ECC decoder in decoding the input code word. The pre-processed code word is decoded using the ECC decoder, and the data is recovered from the decoded pre-processed code word. | 03-21-2013 |

20130117606 | DATA PROTECTION FROM WRITE FAILURES IN NONVOLATILE MEMORY - A method includes calculating redundancy information over a set of data items, and sending the data items for storage in a memory. The redundancy information is retained only until the data items are written successfully in the memory, and then discarded. The data items are recovered using the redundancy information upon a failure in writing the data items to the memory. | 05-09-2013 |

20130121080 | Adaptive Estimation of Memory Cell Read Thresholds - A method for operating a memory ( | 05-16-2013 |

20130170272 | OPTIMIZED THRESHOLD SEARCH IN ANALOG MEMORY CELLS - A method includes storing data in a group of analog memory cells. The memory cells in the group are read using first read thresholds to produce first readout results, and re-read using second read thresholds to produce second readout results. Third read thresholds, which include at least one of the first read thresholds and at least one of the second read thresholds, are defined. Readout performance of the first, second and third read thresholds is evaluated based on the first and second readout results. The first, second or third read thresholds are selected based on the evaluated readout performance, and data recovery is performed using the selected read thresholds. | 07-04-2013 |

20130254635 | Chien Search Using Multiple Basis Representation - A method for decoding an Error Correction Code (ECC) includes accepting coefficients, including at least first and second coefficients, of an Error Locator Polynomial (ELP) that is defined over a vector space and has at least one root that is indicative of a location of an error in a set of bits, which represent data that has been encoded with the ECC. The first coefficient is represented using a first basis of the vector space, and the second coefficient is represented using a second basis of the vector space, different from the first basis. Using processing circuitry, the root of the ELP is identified by applying algebraic operations to the coefficients, such that the algebraic operations are applied to the first coefficient using the first basis, and to the second coefficient using the second basis. The error is corrected responsively to the identified root of the ELP. | 09-26-2013 |

20130258738 | OPTIMIZED THRESHOLD SEARCH IN ANALOG MEMORY CELLS USING SEPARATOR PAGES OF THE SAME TYPE AS READ PAGES - A method includes reading a group of analog memory cells using first explicit read thresholds, to produce first readout results. The group is re-read using second explicit read thresholds, to produce second readout results. The group is read using one or more sets of auxiliary thresholds so as to produce auxiliary readout results, such that the number of the auxiliary thresholds in each set is the same as the number of the first explicit read thresholds and the same as the number of the second explicit read thresholds. A readout performance of third read thresholds, which include at least one of the first explicit read thresholds and at least one of the second explicit read thresholds, is evaluated using the first, second and auxiliary readout results. | 10-03-2013 |

20130272356 | Configurable Encoder for Cyclic Error Correction Codes - Apparatus for encoding includes a first processing stage, which is configured to filter input data with a first set of coefficients belonging to a first generator polynomial representing a first ECC, to produce a first output. A second processing stage is configured to filter the first output using a second set of coefficients belonging to a quotient polynomial, which is defined as a quotient of a second generator polynomial, representing a second ECC, divided by the first generator polynomial, to produce a second output. Ancillary circuitry has first and second operational modes and is coupled to the first and second processing stages so as to generate a first redundancy output corresponding to the first ECC based on the first output when operating in the first mode, and to generate a second redundancy output corresponding to the second ECC based on the second output when operating in the second mode. | 10-17-2013 |

20130283122 | Error Correction Coding Over Multiple Memory Pages - A method for data storage includes encoding each of multiple data items individually using a first Error Correction Code (ECC) to produce respective encoded data items. The encoded data items are stored in a memory. The multiple data items are encoded jointly using a second ECC, so as to produce a code word of the second ECC, and only a part of the code word is stored in the memory. The stored encoded data items are recalled from the memory and the first ECC is decoded in order to reconstruct the data items. Upon a failure to reconstruct a given data item from a respective given encoded data item by decoding the first ECC, the given data item is reconstructed based on the part of the code word of the second ECC and on the encoded data items other than the given encoded data item. | 10-24-2013 |

20130283133 | HIGH-PERFORMANCE ECC DECODER - Methods for Error Correction Code (ECC) decoding include producing syndromes from a set of bits, which represent data that has been encoded with the ECC. An Error Locator Polynomial (ELP) is generated based on the syndromes. At least some of the ELP roots are identified, and the errors indicated by these roots are corrected. Each syndrome may be produced by applying to the bits vector operations in a vector space. Each syndrome is produced by applying vector operations using a different basis of the vector space. The ELP may be evaluated on a given field element by operating on ELP coefficients using serial multipliers, wherein each serial multiplier performs a sequence of multiplication cycles and produces an interim result in each cycle. Responsively to detecting at least one interim result indicating that the given element is not an ELP root, the multiplication cycles are terminated before completion of the sequence. | 10-24-2013 |

20130339815 | Power-Optimized Decoding of Linear Codes - A method includes accepting an input code word, which was produced by encoding data with an Error Correction Code (ECC), for decoding by a hardware-implemented ECC decoder. The input code word is pre-processed to produce a pre-processed code word, such that a first number of bit transitions that occur in the hardware-implemented ECC decoder while decoding the pre-processed code word is smaller than a second number of the bit transitions that would occur in the ECC decoder in decoding the input code word. The pre-processed code word is decoded using the ECC decoder, and the data is recovered from the decoded pre-processed code word. | 12-19-2013 |

20140026010 | PARALLEL CHIEN SEARCH OVER MULTIPLE CODE WORDS - A method for decoding an ECC, in a decoder that includes at least first and second root search units, includes accepting at least first and second Error Locator Polynomials (ELPs) that have been computed over respective first and second code words of the ECC. A criterion depending on the ELPs is evaluated. One of first and second modes is selected based on the criterion. One or more first roots of the first ELP and one or more second roots of the second ELP are found using the selected mode, and the first and second code words are decoded using the first and second roots. In the first mode, the first and second root search units are combined and simultaneously find the first roots. In the second mode, the first and second root search units operate separately, and simultaneously identify the first roots and the second roots, respectively. | 01-23-2014 |

20140053043 | Interference-Aware Assignment of Programming Levels in Analog Memory Cells - A method for data storage includes accepting data for storage in a memory including multiple analog memory cells. For each memory cell, a respective set of nominal analog values is assigned for representing data values to be stored in the memory cell, by choosing the nominal analog values for a given memory cell in a respective range that depends on interference between the given memory cell and at least one other memory cell in the memory. The data is stored in each memory cell using the respective selected set of the nominal analog values. | 02-20-2014 |

20140053046 | CONFIGURABLE ENCODER FOR CYCLIC ERROR CORRECTION CODES - Apparatus for encoding includes a first processing stage, which is configured to filter input data with a first set of coefficients belonging to a first generator polynomial representing a first ECC, to produce a first output. A second processing stage is configured to filter the first output using a second set of coefficients belonging to a quotient polynomial, which is defined as a quotient of a second generator polynomial, representing a second ECC, divided by the first generator polynomial, to produce a second output. Ancillary circuitry has first and second operational modes and is coupled to the first and second processing stages so as to generate a first redundancy output corresponding to the first ECC based on the first output when operating in the first mode, and to generate a second redundancy output corresponding to the second ECC based on the second output when operating in the second mode. | 02-20-2014 |

20140059403 | PARAMETER ESTIMATION USING PARTIAL ECC DECODING - In some embodiments, a method includes accepting a code word of a composite Error Correction Code (ECC), which was produced by encoding data with multiple component ECCs, and which was received with one or more reception parameters. One or more of the component ECCs are decoded, but without fully decoding the code word. The one or more reception parameters are estimated based on the decoded component ECCs. In other embodiments, a method includes accepting a code word of an ECC, which encodes data and which was received with one or more reception parameters. An Error Locator Polynomial (ELP), having one or more roots that indicate respective locations of one or more errors in the code word, is derived from the accepted code word. The one or more reception parameters are estimated based on the ELP. | 02-27-2014 |

20140089754 | SOFT MESSAGE-PASSING DECODER WITH EFFICIENT MESSAGE COMPUTATION - A method includes, in a decoder of an Error Correction Code (ECC), maintaining only aggregated information regarding a set of messages, a function of which is to be reported from a first node to a second node of the decoder. The function of the set is determined and reported using the aggregated information. After reporting the function, one of the messages in the set is replaced with a new message. The aggregated information is updated to reflect the set having the new message, and the function of the set having the new message is determined and reported using the updated aggregated information. | 03-27-2014 |

20140119089 | DATA STORAGE IN ANALOG MEMORY CELLS USING A NON-INTEGER NUMBER OF BITS PER CELL - A method for data storage includes, in a first programming phase, storing first data in a group of analog memory cells by programming the memory cells in the group to a set of initial programming levels. In a second programming phase that is subsequent to the first programming phase, second data is stored in the group by: identifying the memory cells in the group that were programmed in the first programming phase to respective levels in a predefined partial subset of the initial programming levels; and programming only the identified memory cells with the second data, so as to set at least some of the identified memory cells to one or more additional programming levels that are different from the initial programming levels. | 05-01-2014 |

20140149820 | EFFICIENT LDPC CODES - A method includes accepting a definition of a mother Error Correction Code (ECC) that is represented by a set of parity check equations and includes first code words, and a definition of a punctured ECC that includes second code words and is derived from the mother ECC by removal of one or more of the parity check equations and removal of one or more punctured check symbols selected from among check symbols of the first code words. A mother decoder, which is designed to decode the mother ECC by exchanging messages between symbol nodes and check nodes in accordance with a predefined interconnection scheme that represents the mother ECC, is provided. An input code word of the punctured ECC is decoded using the mother decoder by initializing one or more of the symbol nodes and controlling one or more of the messages, and while retaining the interconnection scheme. | 05-29-2014 |

20140164884 | HIGH-PERFORMANCE ECC DECODER - Methods for Error Correction Code (ECC) decoding include producing syndromes from a set of bits, which represent data that has been encoded with the ECC. An Error Locator Polynomial (ELP) is generated based on the syndromes. At least some of the ELP roots are identified, and the errors indicated by these roots are corrected. Each syndrome may be produced by applying to the bits vector operations in a vector space. Each syndrome is produced by applying vector operations using a different basis of the vector space. The ELP may be evaluated on a given field element by operating on ELP coefficients using serial multipliers, wherein each serial multiplier performs a sequence of multiplication cycles and produces an interim result in each cycle. Responsively to detecting at least one interim result indicating that the given element is not an ELP root, the multiplication cycles are terminated before completion of the sequence. | 06-12-2014 |

20140201596 | Adaptation of Analog Memory Cell Read Thresholds Using Partial ECC Syndromes - A method includes storing data that is encoded with an Error Correction Code (ECC) in a group of analog memory cells. The memory cells in the group are read using multiple sets of read thresholds. The memory cells in the group are divided into two or more subsets. N partial syndromes of the ECC are computed, each partial syndrome computed over readout results that were read using a respective set of the read thresholds from a respective subset of the memory cells. For each possible N-bit combination of N bit values at corresponding bit positions in the N partial syndromes, a respective count of the bit positions in which the combination occurs is determined, so as to produce a plurality of counts. An optimal set of read thresholds is calculated based on the counts, and data recovery is performed using the optimal read thresholds. | 07-17-2014 |

20140310534 | DATA SCRAMBLING IN MEMORY DEVICES USING COMBINED SEQUENCES - A method for data storage includes generating a first scrambling sequence and a second scrambling sequence that is different from the first scrambling sequence. A combined sequence, which is equal to a bit-wise XOR between the first and second scrambling sequences, is generated. Data is copied from a first location in a memory in which the data is scrambled using the first scrambling sequence, to a second location in the memory in which the data is to be scrambled using the second scrambling sequence, by reading the data from the first location, scrambling the read data using the combined sequence, and then storing the data in the second location. | 10-16-2014 |

20140317478 | CONFIGURABLE AND LOW POWER ENCODER FOR CYCLIC ERROR CORRECTION CODES - A method for encoding includes receiving input data symbols to be encoded with an Error Correction Code (ECC) so as to produce a code word of the ECC including redundancy symbols. The input data symbols are applied first and second processing stages, such that the first processing stage performs a first polynomial division by a fixed-coefficient polynomial with a first degree of parallelism, and the second processing stage performs a second polynomial division by a configurable-coefficient polynomial with a second degree of parallelism that is smaller than the first degree of parallelism, so as to jointly produce the redundancy symbols. | 10-23-2014 |

20140325310 | THRESHOLD ADJUSTMENT USING DATA VALUE BALANCING IN ANALOG MEMORY DEVICE - A method, in a memory including multiple analog memory cells, includes segmenting a group of the memory cells into a common section and at least first and second dedicated sections. Each dedicated section corresponds to a read threshold that is used for reading a data page to be stored in the group. Data to be stored in the group is jointly balanced over a union of the common section and the first dedicated section, and over the union of the common section and the second dedicated section, to create a balanced page such that for each respective read threshold an equal number of memory cells will be programmed to assume programming levels that are separated by the read threshold. The balanced page is stored to the common and dedicated sections, and the read thresholds are adjusted based on detecting imbalance between data values in readout results of the balanced page. | 10-30-2014 |

20140331106 | CALCULATION OF ANALOG MEMORY CELL READOUT PARAMETERS USING CODE WORDS STORED OVER MULTIPLE MEMORY DIES - A method includes, in a memory that includes two or more memory units, storing a code word of an Error Correction Code (ECC) that is representable by a plurality of check equations, such that a first part of the code word is stored in a first memory unit and a second part of the code word is stored in a second memory unit. A subset of the check equations, which operate only on code word bits belonging to the first part stored in the first memory unit, is identified. The first part of the code word is retrieved from the first memory unit, and a count of the check equations in the identified subset that are not satisfied by the retrieved first part of the code word is evaluated. One or more readout parameters, for readout from the first memory unit, are set depending on the evaluated count. | 11-06-2014 |

20140344519 | DISTORTION CANCELLATION IN 3-D NON-VOLATILE MEMORY - A method in a memory that includes multiple analog memory cells arranged in a three-dimensional (3-D) configuration, includes identifying multiple groups of potentially-interfering memory cells that potentially cause interference to a group of target memory cells. Partial distortion components, which are inflicted by the respective groups of the potentially-interfering memory cells on the target memory cells, are estimated. The partial distortion components are progressively accumulated so as to produce an estimated composite distortion affecting the target memory cells, while retaining only the composite distortion and not the partial distortion components. The target memory cells are read, and the interference in the target memory cells is canceled based on the estimated composite distortion. | 11-20-2014 |

20140347924 | DATA STORAGE IN ANALOG MEMORY CELLS ACROSS WORD LINES USING A NON-INTEGER NUMBER OF BITS PER CELL - A method for data storage includes accepting data for storage in an array of analog memory cells, which are arranged in rows associated with respective word lines. At least a first page of the data is stored in a first row of the array, and at least a second page of the data is stored in a second row of the array, having a different word line from the first row. After storing the first and second pages, a third page of the data is stored jointly in the first and second rows. | 11-27-2014 |

20140351669 | Error Correction Codes for Incremental Redundancy - A method includes accepting input including at least part of a codeword that has been encoded by an ECC defined by a set of parity check equations. The codeword includes data bits and parity bits. A decoding process is applied to the codeword using the data bits and only a first partial subset of parity bits in the input, and using only a second partial subset of equations. Upon a failure to decode the codeword using the partial subsets, the codeword is re-decoded using the data bits and all parity bits in the input, and using all equations. The set of parity check equations is defined such that any parity bit in the codeword appears in multiple equations, and any parity bit in the first partial subset of the parity bits appears in a plurality of equations in the second partial subset of the equations. | 11-27-2014 |