Patent application number | Description | Published |
20120286336 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - Disclosed is a semiconductor device and a method for fabricating the semiconductor device. The method for fabricating the semiconductor device comprises steps of: forming a side cliff in a substrate in accordance with a gate mask pattern, the side cliff being substantially vertical to a substrate surface; forming a dielectric layer on the substrate that comprises the side cliff; etching the dielectric layer to have the dielectric layer left only on the side cliff, as a dielectric wall; and burying the side cliff by a substrate growth, the burying is performed up to a level higher than the upper end of the dielectric wall. | 11-15-2012 |
20120302026 | METHOD FOR FORMING A TRANSISTOR - A method for forming a transistor includes providing a substrate, forming a well region in the substrate, and forming a gate structure on a surface of the well region. The gate structure includes a gate oxide layer on the surface of the well region and a gate on the gate oxide layer. The method further includes forming source/drain regions in the substrate at opposite sides of the gate structure and performing an ion doping to the substrate to adjust a threshold voltage. The ion doping is performed after the source/drain regions are formed to reduce the impact to the diffusion of the ions caused by heat treatments performed before the ion doping. The method further includes heating the substrate after the ion doping at a temperature from about 400° C. to about 500° C. | 11-29-2012 |
20130341688 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - Disclosed is a semiconductor device and a method for fabricating the semiconductor device. The method for fabricating the semiconductor device comprises steps of: forming a side cliff in a substrate in accordance with a gate mask pattern, the side cliff being substantially vertical to a substrate surface; forming a dielectric layer on the substrate that comprises the side cliff; etching the dielectric layer to have the dielectric layer left only on the side cliff, as a dielectric wall; and burying the side cliff by a substrate growth, the burying is performed up to a level higher than the upper end of the dielectric wall. | 12-26-2013 |
20140291759 | MOS TRANSISTOR AND FABRICATION METHOD - MOS transistors and fabrication methods are provided. An exemplary MOS transistor includes a gate structure formed on a semiconductor substrate. A lightly doped region is formed by a light ion implantation in the semiconductor substrate on both sides of the gate structure. A first halo region is formed by a first halo implantation to substantially cover the lightly doped region in the semiconductor substrate. A groove is formed in the semiconductor substrate on the both sides of the gate structure. Prior to forming a source and a drain in the groove, a second halo region is formed in the semiconductor substrate by a second halo implantation performed into a groove sidewall that is adjacent to the gate structure. The second halo region substantially covers the lightly doped region in the semiconductor substrate and substantially covers the groove sidewall that is adjacent to the gate structure. | 10-02-2014 |
20140291799 | SEMICONDUCTOR DEVICE INCLUDING STI STRUCTURE AND FABRICATION METHOD - Semiconductor devices including STI structures and their fabrication methods are provided. A mask layer is provided on a semiconductor substrate and patterned to form an opening in the mask layer to expose a surface portion of the semiconductor substrate. A trench is then formed in the semiconductor substrate by etching along the opening. A first dielectric layer is formed in the trench and has a top surface lower than a top surface of the semiconductor substrate to provide an uncovered sidewall surface of the trench in the semiconductor substrate. An epitaxial layer is formed on the uncovered sidewall surface of the trench in the semiconductor substrate. The epitaxial layer includes a spacing to expose a surface portion of the first dielectric layer. A second dielectric layer is formed on the exposed surface portion of the first dielectric layer to fill the spacing formed in the epitaxial layer. | 10-02-2014 |
20150162444 | TRANSISTOR DEVICE AND FABRICATION METHOD - A transistor and a fabrication method are provided. In an exemplary transistor, a gate structure is formed on a surface of the substrate. A first doped region is formed in the substrate on both sides of the gate structure. An opening is formed in the first doped region. A stress layer is formed in the opening of the first doped region on the both sides of the gate structure. The stress layer has a thickness in the substrate less than a depth of the first doped region. The first doped region has a bottom in the substrate surrounding a bottom of the stress layer. The stress layer further contains a second doped region. The second doped region and the first doped region form a source region or a drain region. | 06-11-2015 |
20150206969 | SEMICONDUCTOR DEVICE, RELATED MANUFACTURING METHOD, AND RELATED ELECTRONIC DEVICE - A semiconductor device may include a semiconductor substrate. The semiconductor device may further include a gate electrode that overlaps the semiconductor substrate. The semiconductor device may further include a channel region that overlaps at least one of the gate electrode and the semiconductor substrate. The semiconductor device may further include a stress adjustment element that contacts the channel region and is positioned between the channel region and a surface of the semiconductor substrate in a direction perpendicular to the surface of the semiconductor substrate. A maximum width of the channel region in a direction parallel to the surface of the semiconductor substrate is greater than a maximum width of the stress adjustment element in the direction parallel to the surface of the semiconductor substrate in a cross-sectional view of the semiconductor device. | 07-23-2015 |
20160079428 | FINFET STRUCTURE AND MANUFACTURE METHOD - A method for forming a FinFET transistor structure includes providing a substrate with a buried oxide layer and a layer of first semiconductor material. One or more fin structures are formed on the first layer of semiconductor material using a hard mask layer. Sidewall spacers are formed on sidewalls of the fin structures and the hard mask layer. An angled oxygen ion implantation is carried out using the hard mask and side walls as the mask. Next, an annealing process is performed to form oxide diffusion regions. Then, the oxide diffusion regions are removed, and the exposed first semiconductor material layer is etched to expose portions of the buried oxide layer. The resulting fin structure has recessed regions formed on the sidewalls, and the fin structure has a bottom portion below the recessed regions that is wider than a top portion. | 03-17-2016 |