Patent application number | Description | Published |
20120166777 | METHOD AND APPARATUS FOR SWITCHING THREADS - Techniques for switching or parking threads in a processor including a plurality of processor cores that share a microcode engine are disclosed. In a dual-core or multi-core system, a front end, (e.g., microcode engine), of the processor cores may be shared by the two or more active threads in order to reduce the area, cost, or the like. A currently running thread may be put to a sleep state and execution of another thread may be initiated when a yield microcode command issues while the currently thread is running. The thread may be resumed on a condition that the second thread goes to a sleep state, yields, exits the processing, etc. Alternatively, a thread may be put to a sleep state when a sleep microcode command issues which is programmed to occur when the thread needs to wait for an event to occur. | 06-28-2012 |
20140181410 | MANAGEMENT OF CACHE SIZE - In response to a processor core exiting a low-power state, a cache is set to a minimum size so that fewer than all of the cache's entries are available to store data, thus reducing the cache's power consumption. Over time, the size of the cache can be increased to account for heightened processor activity, thus ensuring that processing efficiency is not significantly impacted by a reduced cache size. In some embodiments, the cache size is increased based on a measured processor performance metric, such as an eviction rate of the cache. In some embodiments, the cache size is increased at regular intervals until a maximum size is reached. | 06-26-2014 |
20150026406 | SIZE ADJUSTING CACHES BY WAY - A size of a cache of a processing system is adjusted by ways, such that each set of the cache has the same number of ways. The cache is a set-associative cache, whereby each set includes a number of ways. In response to defined events at the processing system, a cache controller changes the number of ways of each set of the cache. For example, in response to a processor core indicating that it is entering a period of reduced activity, the cache controller can reduce the number of ways available in each set of the cache. | 01-22-2015 |
20150026407 | SIZE ADJUSTING CACHES BASED ON PROCESSOR POWER MODE - As a processor enters selected low-power modes, a cache is flushed of data by writing data stored at the cache to other levels of a memory hierarchy. The flushing of the cache allows the size of the cache to be reduced without suffering an additional performance penalty of writing the data at the reduced cache locations to the memory hierarchy. Accordingly, when the cache exits the selected low-power modes, it is sized to a minimum size by setting the number of ways of the cache to a minimum number. In response to defined events at the processing system, a cache controller changes the number of ways of each set of the cache. | 01-22-2015 |
Patent application number | Description | Published |
20100112373 | Anti-Reflective Coatings Comprising Ordered Layers of Nanowires and Methods of Making and Using the Same - The present invention is directed to anti-reflective coatings comprising ordered layers of nanowires, methods to prepare the coatings, and products prepared by the methods. | 05-06-2010 |
20100252955 | Methods of Patterning Substrates Using Microcontact Printed Polymer Resists and Articles Prepared Therefrom - The present invention is directed to methods for patterning substrates using contact printing to form patterns comprising a polymer, using the patterns formed therefrom as resists, and process products formed by the process. | 10-07-2010 |
20110076448 | Methods for Patterning Substrates Using Heterogeneous Stamps and Stencils and Methods of Making the Stamps and Stencils - The present invention is directed to heterogeneous stamp and stencil compositions, methods for patterning substrates using contact printing processes employing the heterogeneous stamps and stencils, and products formed by the contact printing processes. | 03-31-2011 |
20110217220 | Metal Oxide Compositions for Sequestering Carbon Dioxide and Methods of Making and Using the Same - The present invention is directed to methods of sequestering carbon dioxide using metal oxide compositions, methods of making the metal oxide compositions, and articles comprising the metal oxide compositions. | 09-08-2011 |
20110226697 | Functional Nanofibers and Methods of Making and Using the Same - The present invention is directed to functional nanofibers, methods of making the functional nanofibers, and products such as filters and membranes comprising mats of the functional nanofibers. | 09-22-2011 |
20110229750 | Polyolefin Fibers for Use as Battery Separators and Methods of Making and Using the Same - The present invention is directed to battery separators comprising layers of non-woven, melt-blown polyolefin fibers, and methods of making and using the same. | 09-22-2011 |
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20120097329 | Stencils for High-Throughput Micron-Scale Etching of Substrates and Processes of Making and Using the Same - The present invention is directed to stencils for high-throughput, high-resolution etching of substrates and processes of making and using the same. | 04-26-2012 |
20130182328 | Structured Smudge-Resistant Anti-Reflective Coatings and Methods of Making and Using the Same - The present invention is directed to articles comprising smudge-resistant anti-reflective surfaces, and products and devices comprising the articles. | 07-18-2013 |
20140133031 | Anti-Reflective Coatings Comprising Ordered Layers of Nanowires and Methods of Making and Using the Same - The present invention is directed to anti-reflective coatings comprising ordered layers of nanowires, methods to prepare the coatings, and products prepared by the methods. | 05-15-2014 |