Patent application number | Description | Published |
20090261917 | AUXILIARY VARACTOR FOR TEMPERATURE COMPENSATION - Techniques for compensating for the effects of temperature change on voltage controlled oscillator (VCO) frequency are disclosed. In an embodiment, an auxiliary varactor is coupled to an LC tank of the VCO. The auxiliary varactor has a capacitance controlled by a temperature-dependant control voltage to minimize the overall change in VCO frequency with temperature. Techniques for generating the control voltage using digital and analog means are further disclosed. | 10-22-2009 |
20090278620 | VCO CAPACITOR BANK TRIMMING AND CALIBRATION - Techniques are disclosed for trimming a capacitance associated with a capacitor bank for use in a voltage-controlled oscillator (VCO). In an embodiment, each capacitance is sub-divided into a plurality of constituent capacitances. The constituent capacitances may be selectively enabled or disabled to trim the step sizes of the capacitor bank. Further techniques are disclosed for calibrating the trimmable capacitance to minimize step size error for the capacitor bank. | 11-12-2009 |
20100238843 | TRANSFORMER-BASED CMOS OSCILLATORS - Techniques for providing transformer-based CMOS oscillators capable of operation with low voltage power supplies. In an exemplary embodiment, an LC tank is provided at the drains of a transistor pair, and the inductance of the LC tank is mutually magnetically coupled to an inductance between the gates of the transistor pair. A separate complementary transistor pair is also coupled to the LC tank. A further exemplary embodiment provides an LC tank at the gates of a transistor pair, as well as for three-way coupling amongst a tank inductance, an inductance between the gates of the transistor pair, and an inductance between the gates of a complementary transistor pair. | 09-23-2010 |
20120242378 | FREQUENCY DIVIDER CIRCUIT - A frequency divider circuit is described. The frequency divider circuit includes a first cross-coupling. The first cross-coupling includes a first cross-coupled transistor with a first gate. The first gate is separately biased. The first cross-coupling also includes a second cross-coupled transistor with a second gate. The second gate is separately biased. The first gate is coupled to the second cross-coupled transistor and the second gate is coupled to the first cross-coupled transistor. | 09-27-2012 |
20130243113 | GENERATING AND ROUTING A SUB-HARMONIC OF A LOCAL OSCILLATOR SIGNAL - A particular apparatus for generating a local oscillator (LO) signal includes a phase-locked loop (PLL) configured to output a signal having a frequency that is a sub-harmonic of a LO frequency. The apparatus also includes a mixer block having a frequency upconverter configured to upconvert the signal to generate a LO signal having the LO frequency. For example, the PLL may be integrated into a multiple-input multiple-output (MIMO) device and may generate the sub-harmonic signal. The sub-harmonic signal may be routed to each of a plurality of mixer blocks of the MIMO device. Each of the mixer blocks may upconvert the sub-harmonic signal to generate the LO signal. | 09-19-2013 |
20140120851 | DC OFFSET FILTER FOR WIDE BAND BEAMFORMING RECEIVERS - A DC offset filter for wide band beamforming receivers is disclosed. In an exemplary embodiment, an apparatus includes a first mixer configured to down-convert an RF wideband beamformed signal to generate a first baseband wideband beamformed signal, the RF wideband beamformed signal having a beam pattern selected from a plurality of beam patterns, and a notch filter configured to remove DC offset from the first baseband wideband beamformed signal independent of the beam pattern. | 05-01-2014 |
20140132359 | CURRENT REUSE VOLTAGE CONTROLLED OSCILLATOR WITH IMPROVED DIFFERENTIAL OUTPUT - A current reuse voltage controlled oscillator with improved differential output is disclosed. In an exemplary embodiment, an apparatus includes a PMOS transistor and an NMOS transistor coupled together for current reuse and configured to provide differential oscillator outputs. The apparatus also includes a common mode rejection (CMR) circuit coupled between the PMOS and the NMOS transistors, the CMR circuit includes an inductor having a least one tap that can be selectively coupled to a ground to reduce common mode signals at the differential oscillator outputs. | 05-15-2014 |
20140152385 | BIDIRECTIONAL MATCHING NETWORK - A bidirectional matching network is disclosed. In an exemplary embodiment, an apparatus includes a first matching circuit connected in a first signal path between a node and a first amplifier, the first matching circuit configured to translate an off-state impedance of the first amplifier to a first translated off-state impedance. The apparatus also includes a second matching circuit connected in a second signal path between the node and a second amplifier. The second matching circuit configured to translate an off-state impedance of the second amplifier to a second translated off-state impedance. The second translated off-state impedance is configured to reduce power loss associated with a first signal flowing in the first signal path and the first translated off-state impedance is configured to reduce power loss associated with a second signal flowing in the second signal path. | 06-05-2014 |
20140179241 | CONCURRENT MATCHING NETWORK USING TRANSMISSION LINES FOR LOW LOSS - A concurrent matching network using transmission lines for low loss is disclosed. In an exemplary embodiment, an apparatus includes a first ¼ wavelength transmission line configured to couple a first signal path to a common node that is coupled to one or more additional signal paths. The apparatus also includes at least one switch configured to disable the first signal path causing the first ¼ wavelength transmission line to provide a first off-state impedance at the common node. | 06-26-2014 |
20140256376 | WIRELESS DEVICE WITH BUILT-IN SELF TEST (BIST) CAPABILITY FOR TRANSMIT AND RECEIVE CIRCUITS - A wireless device with built-in self test (BIST) capability for testing/calibrating transmit and receive circuits is disclosed. In an exemplary design, an apparatus (e.g., a wireless device or an integrated circuit) includes a first circuit and a second circuit. The first circuit (e.g., a transmitter or a mixer) provides a test signal to at least one transmit path. The test signal is electro-magnetically coupled from the output of the at least one transmit path to a test signal line. For example, the test signal may be provided from the at least one transmit path via at least one antenna feed line to at least one antenna element and may be electro-magnetically coupled from the at least one antenna feed line to the test signal line. The second circuit (e.g., a buffer, a receiver, or a mixer) processes a received test signal from the test signal line. | 09-11-2014 |