Patent application number | Description | Published |
20090193067 | SERVER-BASED RECALCULATION OF VECTOR GRAPHICS - Technologies are described herein for recalculating data-bound vector graphics on a server computer. A drawing program allows formulas to define how external data is utilized modify the attributes of a shape. When a request is received to publish a drawing to a server computer, any formulas are converted to server-optimized formulas. Once the formulas have been converted to server-optimized formulas, a published drawing is generated that includes the server-optimized formulas, a representation of the drawing in a vector format, and data identifying bindings between shapes within the drawing and external data. When a request to view the published drawing is received, the data bindings for the drawing are refreshed. The server-optimized formulas are then recalculated using updated values to generate new values for the shape attributes. The vector representation of the drawing is then updated with the new values and rasterized for display in a browser. | 07-30-2009 |
20090195553 | SERVER-BASED RASTERIZATION OF VECTOR GRAPHICS - Technologies are described herein for high-performance rasterization of a vector graphic on a server computer. A vector graphic loader receives the vector graphic and generates an intermediate data structure from the vector graphic. A vector graphic renderer receives the intermediate data structure and renders the intermediate data structure to a render surface. An imaging component encodes the contents of the render surface to a raster image in a standard image format. The vector graphic loader and the vector graphic renderer are configured for multi-threaded and multi-processor execution on a server computer, which provides high performance. | 08-06-2009 |
20090199081 | WEB-BASED VISUALIZATION, REFRESH, AND CONSUMPTION OF DATA-LINKED DIAGRAMS - Technologies are described herein for refreshing data-linked diagrams on a server computer and viewing and consuming the refreshed diagrams via a Web browser. A drawing program allows equations within a diagram definition to define how external data is utilized to modify the attributes of a diagram element. When the diagram is published to a server computer, the definition is converted to server-legible definition. A published diagram is generated that includes a diagram representation defined by the server-legible definition. Upon a request for the published diagram, the external data is refreshed and the diagram definition is updated. The equations are recalculated to generate new element attributes. The diagram representation is then updated with the new attributes and returned for display by a client Web browser. An interface provides exploration tools and a client API exposes methods for surfacing external data and annotating the diagram. | 08-06-2009 |
20130110937 | REAL TIME DOCUMENT PRESENTATION DATA SYNCHRONIZATION THROUGH GENERIC SERVICE | 05-02-2013 |
Patent application number | Description | Published |
20110152719 | MATERIALS AND METHODS FOR HYPOTHERMIC COLLECTION OF WHOLE BLOOD - The present invention relates to materials and methods for hypothermic collection of whole blood, and components thereof, which can extend the holding time of blood beyond the current useable limit. Additionally, blood can be drawn directly into a hypothermic preservation solution without the addition of standard anticoagulants. This is enabled by providing sustained cellular viability under hypothermic conditions using a nutrient matrix devoid of animal proteins and containing energy substrates, free-radical scavengers, and impermeants that is ionically balanced for storage of biologic materials at low temperatures to prevent cellular stress-induced apoptosis. | 06-23-2011 |
20120040450 | APPARATUSES AND COMPOSITIONS FOR CRYOPRESERVATION OF CELLULAR MONOLAYERS - Provided are apparatuses for cryopreserving cells which include a vessel comprising a biocompatible substrate, wherein the vessel further comprises an interior and an exterior, and a mechanical ice nucleating device disposed in or on the vessel interior for initiating ice crystal formation. Also provided are kits comprising one or more apparatuses for cryopreserving cells and a biopreservation medium. Further provided are compositions comprising a vessel for holding cells, a mechanical ice nucleating device, a biopreservation medium, and cells disposed in the vessel. The apparatuses, kits, and compositions of the invention can optionally include an insulating material which is disposed on all or a portion of the vessel. | 02-16-2012 |
Patent application number | Description | Published |
20090075299 | Diagnostic Methods - The present invention relates to methods of diagnosing cancerous conditions in a patient, as well as methods of monitoring the progression of a cancerous condition and/or methods of monitoring a treatment protocol of a therapeutic agent or a chemotherapeutic regimen. The invention also relates to assay methods used in connection with the diagnostic methods described herein. | 03-19-2009 |
20120046197 | BIOMARKERS OF THERAPEUTIC RESPONSIVENESS - The present invention relates to methods of diagnosing a kidney disorder in a patient, as well as methods of monitoring the progression of a kidney disorder and/or methods of monitoring a treatment protocol of a therapeutic agent or a therapeutic regimen. The invention also relates to assay methods used in connection with the diagnostic methods described herein. | 02-23-2012 |
20120058916 | DIAGNOSTIC METHODS FOR LIVER DISORDERS - The present invention relates to methods of diagnosing a liver disorder in a patient, as well as methods of monitoring the progression of a liver disorder and/or methods of monitoring a treatment protocol of a therapeutic agent or a chemotherapeutic regimen. The invention also relates to assay methods used in connection with the diagnostic methods described herein. | 03-08-2012 |
20140141985 | BIOMARKERS OF THERAPEUTIC RESPONSIVENESS - The present invention relates to methods of diagnosing a kidney disorder in a patient, as well as methods of monitoring the progression of a kidney disorder and/or methods of monitoring a treatment protocol of a therapeutic agent or a therapeutic regimen. The invention also relates to assay methods used in connection with the diagnostic methods described herein. | 05-22-2014 |
20140221368 | BIOMARKERS OF THERAPEUTIC RESPONSIVENESS - The present invention relates to methods of diagnosing breast cancer in a patient, as well as methods of monitoring the progression of breast cancer and/or methods of monitoring a treatment protocol of a therapeutic agent or a therapeutic regimen. The invention also relates to assay methods used in connection with the diagnostic methods described herein. | 08-07-2014 |
20140309263 | BIOMARKERS OF THERAPEUTIC RESPONSIVENESS - The present invention relates to methods of diagnosing a kidney disorder in a patient, as well as methods of monitoring the progression of a kidney disorder and/or methods of monitoring a treatment protocol of a therapeutic agent or a therapeutic regimen. The invention also relates to assay methods used in connection with the diagnostic methods described herein. | 10-16-2014 |
20140315742 | BIODOSIMETRY PANELS AND METHODS - The present invention relates to methods and kits to assess an absorbed dose of ionizing radiation and/or the severity of tissue injury from radiation in a patient. The invention also relates to algorithms used to calculate an absorbed dose of radiation based on biomarker measurements of a plurality of biomarkers that are altered relative to a normal control in the event of radiation exposure. | 10-23-2014 |
Patent application number | Description | Published |
20110202412 | TOUCHLESS AND TOUCH OPTIMIZED PROCESSING OF RETAIL AND OTHER COMMERCE TRANSACTIONS - A computer implemented method for reducing input performed in a commerce based application is provided. The method includes receiving a sequence of input values from an input device and associating the sequence of input values with an object in the application based on the sequence. A context of the application is determined One or more tasks in the application are automatically performed based on the object, the context and the sequence of input values. | 08-18-2011 |
20110313991 | AUTOMATIC SEARCH FUNCTIONALITY WITHIN BUSINESS APPLICATIONS - Disclosed herein is an integration of automatic search functionality into a business application. The application is monitored for an instance wherein the user is initiating an activity that involves an expenditure. Upon detection of such an activity, a query is automatically generated based on information related to the expenditure. The query is communicated to a search component, from which corresponding search results are eventually received. Finally, at least some information related to the search results is displayed to the user. In one embodiment, assuming the user's express or implicit approval, auto-generation of data and/or modification of business process flow are facilitated based on the search results. | 12-22-2011 |
20130185154 | TARGETING OF CONSUMER LISTS UNDER CONSENT BY EXTERNAL PARTIES FOR PROMOTIONS AND DISCOUNTS - A consumer owns a list of items, whether goods or services, including one or more entries, with each entry indicating an item, such as a good or service. This list of items has one or more entries with associated authorizations. The authorizations indicate which entities can access information from the entry in the list, and which actions the entities can perform using the information on the list. In particular, such authorizations include one or forms of targeting of the owner of the list, typically a consumer of goods and services, with promotions, advertisements, discounts, coupons and similar information relating to the goods and services on the list. The consumer controls the content and authorizations in the list. | 07-18-2013 |
Patent application number | Description | Published |
20140300556 | IDENTIFICTION CARD HAVING A PLURALITY OF IMAGES - According to some embodiments, an identification card may be provided with a processor, coupled to a substantially card-shaped body, executing an operating system. A substantially planar display device may also be coupled to the card-shaped body and communicate with the processor to provide visual information to a cardholder. A storage unit, coupled to the card-shaped body and in communication with the processor, may store a plurality of image files. According to some embodiments, execution of the operating system results in a selection of one of the image files to be provided on the display device. | 10-09-2014 |
20150088642 | INTELLIGENT SHOPPING CART SERVICE - Disclosed are methods, apparatus and systems for providing an intelligent shopping cart service that operates to alert a consumer when a product or service is not aligned with the consumer's preferences, criteria or requirements before a purchase transaction is consummated. In some embodiments, a consumer device includes a processor that stores intelligent shopping cart software in a memory, and that uses the intelligent shopping cart software to detect product or service identification data when a consumer adds a product or service to a shopping cart. The processor then determines, based on the product or service identification data, that the product or service is a mismatch when compared to predetermined consumer preferences, criteria or requirements. An alert indication is then provided to the consumer via an output component before a purchase transaction is consummated. | 03-26-2015 |
Patent application number | Description | Published |
20080214338 | Bat With Flexible Handle - Included herein is a bat for striking a ball. The bat comprises a barrel portion, transition portion attached to the barrel portion, and a handle portion attached to the transition portion. The handle portion includes a longitudinal axis and a plurality of planes substantially parallel to the axis. The adjacent planes of the plurality of planes are positioned to define apertures substantially parallel to the axis. The planes and apertures are positioned to vary the flexibility of the handle and improve bat performance for a given swing speeds. | 09-04-2008 |
20090253540 | Bat With Flexible Handle - Included herein is a bat for striking a ball. The bat comprises a barrel portion, transition portion attached to the barrel portion, and a handle portion attached to the transition portion. The handle portion includes a longitudinal axis and a plurality of planes substantially parallel to the axis. The adjacent planes of the plurality of planes are positioned to define apertures substantially parallel to the axis. The planes and apertures are positioned to vary the flexibility of the handle and improve bat performance for a given swing speeds. | 10-08-2009 |
20100009787 | Bat With Flexible Handle - Included herein is a bat for striking a ball. The bat comprises a barrel portion, transition portion attached to the barrel portion, and a handle portion attached to the transition portion. The handle portion includes a longitudinal axis and a plurality of planes substantially parallel to the axis. The adjacent planes of the plurality of planes are positioned to define apertures substantially parallel to the axis. The planes and apertures are positioned to vary the flexibility of the handle and improve bat performance for a given swing speeds. | 01-14-2010 |
Patent application number | Description | Published |
20080235277 | System and method for temporal recall of related items in an information workspace - A system and method are described for recording events in different applications within a workspace. For example, a system according to one embodiment of the invention comprises: an action recorder module for generating event records representing actions performed by a user in a plurality of different applications over a period of time; a storage unit for storing the event records; a past time selector module to select a past time period of recorded event records in response to user input; an event recaller module to retrieve event records related to each of the applications over the past time period from the storage unit; and a graphical user interface to graphically display actions associated with event records occurring in each of the applications over the past time period, the graphical user interface arranged to illustrate a temporal relationship between actions occurring in each of the different applications. | 09-25-2008 |
20090129572 | Billing data interface for conferencing customers - A billing data interface provides billing data to customers in an accurate and efficient manner. Billing data is processed to preserve client billing information and to meet a customer's individual data requirements. The billing data may be presented in such a way that the customer may input the billing data directly into its client billing system. The billing data may be processed according to client billing specifications corresponding to a client billing system used by the customer. The processed data may preserve leading zeros, separate client code and matter code into two fields, etc. The resulting data file may be delivered to the customer for entry into the customer's client billing system. | 05-21-2009 |
20110004619 | DYNAMIC REPORTING TOOL FOR CONFERENCING CUSTOMERS - A dynamic reporting tool presents conferencing data to customers in a useful and flexible manner. Customers may customize standard reports using dynamic, comprehensive search criteria. Customers may also create custom ad hoc reports as needed. Furthermore, customers may access unbilled usage data and conduct searches on the unbilled usage data. | 01-06-2011 |
20110261936 | Online reporting tool for conferencing customers - Embodiments consistent with the present invention provide an integrated system for conferencing services reporting to support customer billing needs. Systems consistent with the present invention enable a customer to retrieve and use integrated usage data, including data for unbilled conferencing services. Furthermore, systems consistent with the present invention provide an integrated account management interface to enable a customer to retrieve and use account information in real time and to manage a conferencing services account with ease. Still further, systems consistent with the present invention enable a customer to establish multiple levels of security to easily manage multiple users with multiple information needs and responsibilities. Systems consistent with the present invention also provide tools to analyze and track moderator conferencing schedules to enhance accurate timekeeping and billing. | 10-27-2011 |
20120057686 | BILLING DATA INTERFACE FOR CONFERENCING CUSTOMERS - A billing data interface provides billing data to customers in an accurate and efficient manner. Billing data is processed to preserve client billing information and to meet a customer's individual data requirements. The billing data may be presented in such a way that the customer may input the billing data directly into its client billing system. The billing data may be processed according to client billing specifications corresponding to a client billing system used by the customer. The processed data may preserve leading zeros, separate client code and matter code into two fields, etc. The resulting data file may be delivered to the customer for entry into the customer's client billing system. | 03-08-2012 |
Patent application number | Description | Published |
20090048290 | 2S,3R)-N-(2-((3-PYRIDINYL)METHYL)-1-AZABICYCLO[2.2.2]OCT-3-YL-BENZYOFURAN-- 2-CARBOXAMIDE, NOVEL SALT FORMS, AND METHODS OF USE THEREOF - The present invention relates to (2S,3R)—N-(2-((3-pyridinyl)methyl)-1-azabicyclo[2.2.2]oct-3-yl)benzofuran-2-carboxamide, novel salt forms thereof, methods for its preparation, novel intermediates, and methods for treating a wide variety of conditions and disorders, including those associated with dysfunction of the central and autonomic nervous systems. | 02-19-2009 |
20110118239 | PREPARATION AND ENANTIOMERIC SEPARATION OF 7-(3-PYRIDINYL)-1,7-DIAZASPIRO[4.4]NONANE AND NOVEL SALT FORMS OF THE RACEMATE AND ENANTIOMERS - A novel scalable synthesis for the preparation of 7-(3-pyridinyI)-1,7-diazaspiro[4.4)nonane has been developed, and 7-(3-pyridinyl)-1,7-diazaspiro[4.4]nonane salts have been formed with succinic acid and oxalic acid. Additionally, 7-(3-pyridinyl)-1,7-diaza-spiro[4.4]nonane has been separated into its stereoisomers via resolution with L and D di-p-toluoyltartaric acids, giving (R)- and (S)-7-(3-pyridinyl)-1,7-diazaspiro[4.4]nonane of high enantiomeric purity. Numerous solid salts of the resulting (R)- and (S)-7-(3-pyridinyl)-1,7-diazaspiro[4.4}nonane have been prepared. Methods for the preparation of the racemic and enantiomeric salts, pharmaceutical compositions comprising such salts, and uses thereof are disclosed. The salts can be administered to patients susceptible to or suffering from conditions and disorders, such as central nervous system disorders, to treat and/or prevent such disorders. | 05-19-2011 |
20110263859 | (2S, 3R)-N-(2-((3-PYRIDINYL)METHYL)-1-AZABICYCLO[2.2.2]OCT-3-YL)BENZOFURAN- -2-CARBOXAMIDE, NOVEL SALT FORMS, AND METHODS OF USE THEREOF - The present invention relates to (2S,3R)-N-(2((3-pyridiny)triethyl)-1-azabicyclo[2.2.2]oct-3-yl)benzofuran-2-carboxamide, novel salt forms thereof, methods for its preparation, novel intermediates, and methods for treating a wide variety of conditions and disorders, including those associated with dysfunction of the central and autonomic nervous systems. | 10-27-2011 |
Patent application number | Description | Published |
20080246124 | PLASMA TREATMENT OF INSULATING MATERIAL - A method is disclosed which includes forming an opening in an insulating material, performing a plasma process to introduce nitrogen into a portion of the insulating material to thereby form a nitrogen-containing region at least on an inner surface of the opening, and, after forming the nitrogen-containing region, performing an etching process through the opening. A device is disclosed which includes an insulating material comprising a nitrogen-enhanced region that is proximate an opening that extends through the insulating material and a conductive structure positioned within the opening. | 10-09-2008 |
20090176365 | CONTACT FORMATION - The present disclosure includes various method, circuit, device, and system embodiments. One such method embodiment includes creating a trench in an insulator stack material having a portion of the trench positioned between two of a number of gates and depositing a spacer material to at least one side surface of the trench. This method also includes depositing a conductive material into the trench and depositing a cap material into the trench. | 07-09-2009 |
20100233875 | CONTACT FORMATION - The present disclosure includes various method of contact embodiments. One such method embodiment includes creating a trench in an insulator stack material of a particular thickness and having a portion of the trench positioned between two of a number of gates. This method includes depositing a filler material in the trench and etching the filler material to a particular depth that is less than the particular thickness of the insulator stack material. This method also includes depositing a spacer material to at least one side surface of the trench to the particular depth of the filler material and depositing a conductive material into the trench over the filler material. | 09-16-2010 |
20120009779 | CONTACT FORMATION - The present disclosure includes various methods of contact embodiments. One such method embodiment includes forming a trench in an insulator stack material of a particular thickness. This method includes forming a filler material in the trench and removing the filler material to a particular depth that is less than the particular thickness of the insulator stack material. This method also includes forming a spacer material on at least one side surface of the trench to the particular depth of the filler material and forming a conductive material in the trench over the filler material. | 01-12-2012 |
20130087883 | Integrated Circuit Devices And Methods Of Forming Memory Array And Peripheral Circuitry Isolation - A method of forming memory array and peripheral circuitry isolation includes chemical vapor depositing a silicon dioxide-comprising liner over sidewalls of memory array circuitry isolation trenches and peripheral circuitry isolation trenches formed in semiconductor material. Dielectric material is flowed over the silicon dioxide-comprising liner to fill remaining volume of the array isolation trenches and to form a dielectric liner over the silicon dioxide-comprising liner in at least some of the peripheral isolation trenches. The dielectric material is furnace annealed at a temperature no greater than about 500° C. The annealed dielectric material is rapid thermal processed to a temperature no less than about 800° C. A silicon dioxide-comprising material is chemical vapor deposited over the rapid thermal processed dielectric material to fill remaining volume of said at least some peripheral isolation trenches. Other aspects are disclosed, including integrated circuitry resulting from the disclosed methods and integrated circuitry independent of method of manufacture. | 04-11-2013 |
20130168756 | SOURCE/DRAIN ZONES WITH A DELECTRIC PLUG OVER AN ISOLATION REGION BETWEEN ACTIVE REGIONS AND METHODS - Devices, memory arrays, and methods are disclosed. In an embodiment, one such device has a source/drain zone that has first and second active regions, and an isolation region and a dielectric plug between the first and second active regions. The dielectric plug may extend below upper surfaces of the first and second active regions and may be formed of a dielectric material having a lower removal rate than a dielectric material of the isolation region for a particular isotropic removal chemistry. | 07-04-2013 |
20130249050 | INTEGRATED CIRCUIT DEVICES AND METHODS OF FORMING MEMORY ARRAY AND PERIPHERAL CIRCUITRY ISOLATION - A method of forming memory array and peripheral circuitry isolation includes chemical vapor depositing a silicon dioxide-comprising liner over sidewalls of memory array circuitry isolation trenches and peripheral circuitry isolation trenches formed in semiconductor material. Dielectric material is flowed over the silicon dioxide-comprising liner to fill remaining volume of the array isolation trenches and to form a dielectric liner over the silicon dioxide-comprising liner in at least some of the peripheral isolation trenches. The dielectric material is furnace annealed at a temperature no greater than about 500° C. The annealed dielectric material is rapid thermal processed to a temperature no less than about 800° C. A silicon dioxide-comprising material is chemical vapor deposited over the rapid thermal processed dielectric material to fill remaining volume of said at least some peripheral isolation trenches. Other aspects are disclosed, including integrated circuitry resulting from the disclosed methods and integrated circuitry independent of method of manufacture. | 09-26-2013 |
20140027832 | FORMING AIR GAPS IN MEMORY ARRAYS AND MEMORY ARRAYS WITH AIR GAPS THUS FORMED - A memory array has first and second memory cells over a semiconductor and an isolation region extending into the semiconductor. The isolation region includes an air gap between charge-storage structures of the first and second memory cells and a thickness of dielectric over the air gap and contained between the first and second memory cells. | 01-30-2014 |
Patent application number | Description | Published |
20090075271 | Methods of identifying individuals at risk of perioperative bleeding, renal dysfunction or stroke - The present invention relates, in general, to perioperative bleeding and, in particular, to methods of identifying individuals at risk of perioperative bleeding. | 03-19-2009 |
20090155792 | PREDICTORS OF LONG-TERM MORTALITY FOLLOWING CORONARY ARTERY BYPASS GRAFT SURGERY - The present invention relates, in general, to perioperative depression and, in particular, to methods of identifying individuals at risk of perioperative depression. | 06-18-2009 |
20100047775 | Method of identifying individuals at risk of perioperative myocardial injury, major adverse cardiac events, cognitive decline, arrhythmias, depression or bleeding - The present invention relates to methods of identifying individuals at risk of perioperative myocardial injury, major adverse cardiac events, cognitive decline, arrhythmias, depression and bleeding. | 02-25-2010 |
20120322667 | METHODS OF IDENTIFYING INDIVIDUALS AT RISK OF PERIOPERATIVE BLEEDING, RENAL DYSFUNCTION OR STROKE - The present invention relates, in general, to perioperative bleeding and, in particular, to methods of identifying individuals at risk of perioperative bleeding. | 12-20-2012 |
20140141429 | METHODS OF IDENTIFYING INDIVIDUALS AT RISK OF PERIOPERATIVE BLEEDING, RENAL DYSFUNCTION OR STROKE - The present invention relates, in general, to perioperative bleeding and, in particular, to methods of identifying individuals at risk of perioperative bleeding. | 05-22-2014 |
Patent application number | Description | Published |
20100233730 | THERAPEUTIC MODULATION OF AUTOPHAGY - Methods for screening for modulators of autophagy are disclosed. Methods for identifying genes whose expression inhibits autophagy, as well as genes whose expression promotes autophagy, are disclosed. Also disclosed are methods for identifying compounds that stimulate autophagy, as well as compounds that inhibit autophagy. Cell lines that may be used in the methods of identification are also disclosed. | 09-16-2010 |
20120202707 | CELL LINES USEFUL FOR ASSESSING MODULATION OF AUTOPHAGY - Methods for screening for modulators of autophagy are disclosed. Methods for identifying genes whose expression inhibits autophagy, as well as genes whose expression promotes autophagy, are disclosed. Also disclosed are methods for identifying compounds that stimulate autophagy, as well as compounds that inhibit autophagy. Cell lines that may be used in the methods of identification are also disclosed. | 08-09-2012 |
20140134661 | THERAPEUTIC MODULATION OF AUTOPHAGY - Methods for screening for modulators of autophagy are disclosed. Methods for identifying genes whose expression inhibits autophagy, as well as genes whose expression promotes autophagy, are disclosed. Also disclosed are methods for identifying compounds that stimulate autophagy, as well as compounds that inhibit autophagy. Cell lines that may be used in the methods of identification are also disclosed. | 05-15-2014 |
Patent application number | Description | Published |
20090176804 | 2-PHENYL-INDOLES AS PROSTAGLANDIN D2 RECEPTOR ANTAGONISTS - The present invention is directed to 2-phenyl-indole compounds, their preparation, pharmaceutical compositions containing these compounds, and their pharmaceutical use in treating a patient suffering from a PGD2-mediated disorder including, but not limited to, allergic disease (such as allergic rhinitis, allergic conjunctivitis, atopic dermatitis, bronchial asthma and food allergy), systemic mastocytosis, disorders accompanied by systemic mast cell activation, anaphylaxis shock, bronchoconstriction, bronchitis, eczema, urticaria diseases accompanied by itch (such as atopic dermatitis and urticaria), diseases (such as cataract, retinal detachment, inflammation, infection and sleeping disorders) which are generated secondarily as a result of behavior accompanied by itch (such as scratching and beating), inflammation, chronic obstructive pulmonary diseases, ischemic reperfusion injury, cerebrovascular accident, chronic rheumatoid arthritis, pleurisy, ulcerative colitis and the like. | 07-09-2009 |
Patent application number | Description | Published |
20090003589 | Native Composite-Field AES Encryption/Decryption Accelerator Circuit - A system comprises reception of input data of a Galois field GF(2 | 01-01-2009 |
20140028677 | GRAPHICS LIGHTING ENGINE INCLUDING LOG AND ANTI-LOG UNITS - Disclosed is an apparatus and method for generating a lighting value based on a number of lighting factors. A lighting accelerator first converts an ambient portion, a diffuse light portion, and a specular light portion of the lighting factors into the log domain. Then, data combination units operate on the lighting factors after they have been converted. Then, the lighting factors are converted back from the log domain using anti-log processing. Converting the lighting factors into the log domain is accomplished by using a series of linear equations using coefficients that are all based on powers of two, and are therefore easily calculable. Further, while in the log domain, the specular light portion of the lighting factor is operated on by a special purpose multiplier that uses a truncated partial product tree, saving area and power with only a negligible amount of error. | 01-30-2014 |
20150086007 | COMPACT, LOW POWER ADVANCED ENCRYPTION STANDARD CIRCUIT - Embodiments of an invention for a compact, low power Advanced Encryption Standard circuit are disclosed. In one embodiment, an apparatus includes an encryption unit having a substitution box and an accumulator. The substitution box is to perform a substitution operation on one byte per clock cycle. The accumulator is to accumulate four bytes and perform a mix-column operation in four clock cycles. The encryption unit is implemented using optimum Galois Field polynomial arithmetic for minimum area. | 03-26-2015 |
Patent application number | Description | Published |
20080238736 | BINARY-TO-BCD CONVERSION - Disclosed herein are various embodiments of circuitry and methods to convert from a binary value to a BCD value. | 10-02-2008 |
20090167351 | CO-PROCESSOR HAVING CONFIGURABLE LOGIC BLOCKS - A co-processor system is provided that includes an array of configurable logic blocks (CLBs). Each CLB including a plurality of look-up tables and a plurality of adders. Each CLB may be dynamically reconfigurable to perform a plurality of logical functions. | 07-02-2009 |
20090172068 | METHOD AND APPARATUS FOR EFFICIENTLY IMPLEMENTING THE ADVANCED ENCRYPTION STANDARD - Implementations of Advanced Encryption Standard (AES) encryption and decryption processes are disclosed. In one embodiment of S-box processing, a block of 16 byte values is converted, each byte value being converted from a polynomial representation in GF(256) to a polynomial representation in GF((2 | 07-02-2009 |
20100082718 | COMBINED SET BIT COUNT AND DETECTOR LOGIC - A merged datapath for PopCount and BitScan is described. A hardware circuit includes a compressor tree utilized for a PopCount function, which is reused by a BitScan function (e.g., bit scan forward (BSF) or bit scan reverse (BSR)). Selector logic enables the compressor tree to operate on an input word for the PopCount or BitScan operation, based on a microprocessor instruction. The input word is encoded if a BitScan operation is selected. The compressor tree receives the input word, operates on the bits as though all bits have same level of significance (e.g., for an N-bit input word, the input word is treated as N one-bit inputs). The result of the compressor tree circuit is a binary value representing a number related to the operation performed (the number of set bits for PopCount, or the bit position of the first set bit encountered by scanning the input word). | 04-01-2010 |
20110158403 | ON-THE-FLY KEY GENERATION FOR ENCRYPTION AND DECRYPTION - Methods and apparatus to provide on-the-fly key computation for Galois Field (also referred to Finite Field) encryption and/or decryption are described. In one embodiment, logic generates a cipher key, in a second cycle, based on a previous cipher key, generated in a first cycle that immediately precedes the second cycle. Other embodiments are also described. | 06-30-2011 |
20120072703 | SPLIT PATH MULTIPLY ACCUMULATE UNIT - In one embodiment, a processor includes a multiply-accumulate (MAC) unit having a first path to handle execution of an instruction if a difference between at least a portion of first and second operands and a third operand is less than a threshold value, and a second path to handle the instruction execution if the difference is greater than the threshold value. Based on the difference, at least part of the third operand is to be provided to a multiplier of the MAC unit or to a compressor of the second path. Other embodiments are described and claimed. | 03-22-2012 |
20120328097 | APPARATUS AND METHOD FOR SKEIN HASHING - Described herein are an apparatus and method for Skein hashing. The apparatus comprises a block cipher operable to receive an input data and to generate a hashed output data by applying Unique Block Iteration (UBI) modes, the block cipher comprising at least two mix and permute logic units which are pipelined by registers; and a counter, coupled to the block cipher, to determine a sequence of the UBI modes and to cause the block cipher to process at least two input data simultaneously for generating the hashed output data. | 12-27-2012 |
20140091832 | INTEGRATED CIRCUITS HAVING ACCESSIBLE AND INACCESSIBLE PHYSICALLY UNCLONABLE FUNCTIONS - An integrated circuit substrate of an aspect includes a plurality of exposed electrical contacts. The integrated circuit substrate also includes an inaccessible set of Physically Unclonable Function (PUF) cells to generate an inaccessible set of PUF bits that are not accessible through the exposed electrical contacts. The integrated circuit substrate also includes an accessible set of PUF cells to generate an accessible set of PUF bits that are accessible through the exposed electrical contacts. Other apparatus, methods, and systems are also disclosed. | 04-03-2014 |
20140188968 | VARIABLE PRECISION FLOATING POINT MULTIPLY-ADD CIRCUIT - Embodiments of the present invention may provide methods and circuits for energy efficient floating point multiply and/or add operations. A variable precision floating point circuit may determine the certainty of the result of a multiply-add floating point calculation in parallel with the floating-point calculation. The variable precision floating point circuit may use the certainty of the inputs in combination with information from the computation, such as, binary digits that cancel, normalization shifts, and rounding, to perform a calculation of the certainty of the result. A floating point multiplication circuit may determine whether a lowest portion of a multiplication result could affect the final result and may induce a replay of the multiplication operation when it is determined that the result could affect the final result. | 07-03-2014 |
20140201540 | SECURE KEY STORAGE USING PHYSICALLY UNCLONABLE FUNCTIONS - Some implementations disclosed herein provide techniques and arrangements for provisioning keys to integrated circuits/processors. A processor may include physically unclonable functions component, which may generate a unique hardware key based at least on at least one physical characteristic of the processor. The hardware key may be employed in encrypting a key such as a secret key. The encrypted key may be stored in a memory of the processor. The encrypted key may be validated. The integrity of the key may be protected by communicatively isolating at least one component of the processor. | 07-17-2014 |
20140218067 | GROUPING OF PHYSICALLY UNCLONABLE FUNCTIONS - A physically unclonable function (PUF) includes a plurality of PUF elements to generate an N-bit PUF signature. For each bit in the N-bit PUF signature, a PUF group of K number of individual PUF elements indicating a single-bit PUF value is used to generate a group bit. The group bits are more repeatable than the individual PUF elements. The value K may be selected such that (K+ | 08-07-2014 |
20140266297 | HARDWARE-EMBEDDED KEY BASED ON RANDOM VARIATIONS OF A STRESS-HARDENED INEGRATED CIRCUIT - An IC cell designed to assert one of multiple possible output states, each with equal probability, implemented to assert a pre-determined one of the multiple output states based on random variations within the IC cell, such as random process variations. An array of IC cells is configurable to provide a hardware-embedded key upon power-up that is unique to the combination of random variations of selected IC cells, resistant to tampering prior to and during manufacture, and tolerant to aging, instantaneous thermal noise, and environmental variations, such as voltage and temperature fluctuations. The key may be used as, without limitation, a Platform Root Key, a High-Bandwidth Digital Content Protection (HDCP) key, an Enhanced Privacy Identification (EPID) key, and/or an Advanced Access Content System (AACS) key. Also disclosed are techniques to measure stability and stress-harden an IC cell based on output states of the IC cell. | 09-18-2014 |
20150023500 | APPARATUS AND METHOD FOR SKEIN HASHING - Described herein are an apparatus and method for Skein hashing. The apparatus comprises a block cipher operable to receive an input data and to generate a hashed output data by applying Unique Block Iteration (UBI) modes, the block cipher comprising at least two mix and permute logic units which are pipelined by registers; and a counter, coupled to the block cipher, to determine a sequence of the UBI modes and to cause the block cipher to process at least two input data simultaneously for generating the hashed output data. | 01-22-2015 |
Patent application number | Description | Published |
20090218081 | Composite Heat Exchanger End Structure - A heat exchanger having a tube bundle disposed within a housing with a resilient end structure disposed in compressed, plug-forming relation at least partially across the heat exchanging cavity. The resilient end structure includes one or more boundary segments extending between an internal wall of the housing and the perimeter of the tube bundle. The boundary segment includes a combination of materials having differing compression characteristics providing enhanced support to the boundary segments. | 09-03-2009 |
20130045040 | Pin Joint Having an Elastomeric Bushing - An elastomeric bushing can be incorporated into a pin joint assembly of a machine. The elastomeric bushing can be configured to allow at least three degrees of relative rotational movement, including roll, pitch, and yaw. The elastomeric bushing can rotate with respect to a pin about a longitudinal axis thereof. The elastomeric bushing is adapted to accommodate out-of-plane movement. The elastomeric bushing can include a plurality of alternating elastomeric layers and metal plies. | 02-21-2013 |
20140286693 | Boot Seal For Machine System And Method - A machine system includes a first component, a second component, and a joint assembly pivotably connecting the first and second components in a finite angular pivoting range. A boot seal seals between the first and second components, and has a rest configuration where the boot seal has a curvilinear taper, and is deformable to a squished configuration forming a radially outward bulge. The radially outward bulge stores an energy of compression of the boot seal, to bias a sealing ring in the boot seal against the second component. | 09-25-2014 |
Patent application number | Description | Published |
20090190394 | CAPACITORLESS DRAM ON BULK SILICON - A method of forming capacitorless DRAM over localized silicon-on-insulator comprises the following steps: A silicon substrate is provided, and an array of silicon studs is defined within the silicon substrate. An insulator layer is defined atop at least a portion of the silicon substrate, and between the silicon studs. A silicon-over-insulator layer is defined surrounding the silicon studs atop the insulator layer, and a capacitorless DRAM is formed within and above the silicon-over-insulator layer. | 07-30-2009 |
20110020988 | CAPACITORLESS DRAM ON BULK SILICON - A method of forming capacitorless DRAM over localized silicon-on-insulator comprises the following steps: A silicon substrate is provided, and an array of silicon studs is defined within the silicon substrate. An insulator layer is defined atop at least a portion of the silicon substrate, and between the silicon studs. A silicon-over-insulator layer is defined surrounding the silicon studs atop the insulator layer, and a capacitorless DRAM is formed within and above the silicon-over-insulator layer. | 01-27-2011 |
20110117725 | Methods of Forming Recessed Access Devices Associated with Semiconductor Constructions - The invention includes methods of forming recessed access devices. A substrate is provided to have recessed access device trenches therein. A pair of the recessed access device trenches are adjacent one another. Electrically conductive material is formed within the recessed access device trenches, and source/drain regions are formed proximate the electrically conductive material. The electrically conductive material and source/drain regions together are incorporated into a pair of adjacent recessed access devices. After the recessed access device trenches are formed within the substrate, an isolation region trench is formed between the adjacent recessed access devices and filled with electrically insulative material to form a trenched isolation region. | 05-19-2011 |
20110198708 | TRANSISTORS HAVING ARGON GATE IMPLANTS AND METHODS OF FORMING THE SAME - Transistors are provided including first and second source/drain regions, a channel region and a gate stack having a first gate dielectric over a substrate, the first gate dielectric having a dielectric constant higher than a dielectric constant of silicon dioxide, and a metal material in contact with the first gate dielectric, the metal material being doped with an inert element. Integrated circuits including the transistors and methods of forming the transistors are also provided. | 08-18-2011 |
20120009772 | Gate Constructions Of Recessed Access Devices And Methods Of Forming Gate Constructions Of Recessed Access Devices - A method of forming a gate construction of a recessed access device includes forming a pair of sidewall spacers laterally over opposing sidewalls of a gate dielectric and elevationally over first conductive gate material. The gate dielectric, the first conductive gate material, and the sidewall spacers are received within a trench formed in semiconductive material. Second conductive gate material is deposited within the semiconductive material trench between the pair of sidewall spacers in electrical connection with the first conductive gate material. Other implementations are disclosed, including recessed access device gate constructions independent of method of manufacture. | 01-12-2012 |
20120199908 | CAPACITORLESS DRAM ON BULK SILICON - A method of forming capacitorless DRAM over localized silicon-on-insulator comprises the following steps: A silicon substrate is provided, and an array of silicon studs is defined within the silicon substrate. An insulator layer is defined atop at least a portion of the silicon substrate, and between the silicon studs. A silicon-over-insulator layer is defined surrounding the silicon studs atop the insulator layer, and a capacitorless DRAM is formed within and above the silicon-over-insulator layer. | 08-09-2012 |
20130187279 | SEMICONDUCTOR DEVICE STRUCTURES INCLUDING BURIED DIGIT LINES AND RELATED METHODS - Methods of forming semiconductor device structures include forming trenches in an array region and in a buried digit line end region, forming a metal material in the trenches, filling the trenches with a mask material, removing mask material in the trenches to expose a portion of the metal material, and removing the exposed portion of the metal material. A plurality of conductive contacts are formed in direct contact with the metal material in the buried digit line end region. Methods of forming a buried digit line contact include forming conductive contacts physically contacting metal material in trenches in a buried digit line end region. Vertical memory devices and apparatuses include metallic connections disposed between a buried digit line and a conductive contact in a buried digit line end region. | 07-25-2013 |
20130279277 | CAPACITORLESS DRAM ON BULK SILICON - A method of forming capacitorless DRAM over localized silicon-on-insulator comprises the following steps: A silicon substrate is provided, and an array of silicon studs is defined within the silicon substrate. An insulator layer is defined atop at least a portion of the silicon substrate, and between the silicon studs. A silicon-over-insulator layer is defined surrounding the silicon studs atop the insulator layer, and a capacitorless DRAM is formed within and above the silicon-over-insulator layer. | 10-24-2013 |
20140377919 | CMOS FABRICATION - A method of manufacturing a memory device includes an nMOS region and a pMOS region in a substrate. A first gate is defined within the nMOS region, and a second gate is defined in the pMOS region. Disposable spacers are simultaneously defined about the first and second gates. The nMOS and pMOS regions are selectively masked, one at a time, and LDD and Halo implants performed using the same masks as the source/drain implants for each region, by etching back spacers between source/drain implant and LDD/Halo implants. All transistor doping steps, including enhancement, gate and well doping, can be performed using a single mask for each of the nMOS and pMOS regions. Channel length can also be tailored by trimming spacers in one of the regions prior to source/drain doping. | 12-25-2014 |
Patent application number | Description | Published |
20120012892 | HIGH DENSITY THYRISTOR RANDOM ACCESS MEMORY DEVICE AND METHOD - Memory devices and methods of making memory devices are shown. Methods and configurations as shown provide folded and vertical memory devices for increased memory density. Methods provided allow trace wiring in a memory array to be formed on or near a surface of a memory device. | 01-19-2012 |
20120214285 | Methods Of Forming A Vertical Transistor And At Least A Conductive Line Electrically Coupled Therewith, Methods Of Forming Memory Cells, And Methods Of Forming Arrays Of Memory Cells - Trenches are formed into semiconductive material. Masking material is formed laterally over at least elevationally inner sidewall portions of the trenches. Conductivity modifying impurity is implanted through bases of the trenches into semiconductive material there-below. Such impurity is diffused into the masking material received laterally over the elevationally inner sidewall portions of the trenches and into semiconductive material received between the trenches below a mid-channel portion. An elevationally inner source/drain is formed in the semiconductive material below the mid-channel portion. The inner source/drain portion includes said semiconductive material between the trenches which has the impurity therein. A conductive line is formed laterally over and electrically coupled to at least one of opposing sides of the inner source/drain. A gate is formed elevationally outward of and spaced from the conductive line and laterally adjacent the mid-channel portion. Other embodiments are disclosed. | 08-23-2012 |
20130009208 | HIGH DENSITY THYRISTOR RANDOM ACCESS MEMORY DEVICE AND METHOD - Memory devices and methods of making memory devices are shown. Methods and configurations as shown provide folded and vertical memory devices for increased memory density. Methods provided allow trace wiring in a memory array to be formed on or near a surface of a memory device. | 01-10-2013 |
20130087840 | Memory Cells And Methods Of Forming Memory Cells - A memory cell includes a transistor device comprising a pair of source/drains, a body comprising a channel, and a gate construction operatively proximate the channel. The memory cell includes a capacitor comprising a pair of capacitor electrodes having a capacitor dielectric there-between. One of the capacitor electrodes is the channel or is electrically coupled to the channel. The other of the capacitor electrodes includes a portion of the body other than the channel. Methods are also disclosed. | 04-11-2013 |
20130164897 | TRANSISTORS HAVING ARGON GATE IMPLANTS AND METHODS OF FORMING THE SAME - Transistors are provided including first and second source/drain regions, a channel region and a gate stack having a first gate dielectric over a substrate, the first gate dielectric having a dielectric constant higher than a dielectric constant of silicon dioxide, and a metal material in contact with the first gate dielectric, the metal material being doped with an inert element. Integrated circuits including the transistors and methods of forming the transistors are also provided. | 06-27-2013 |
20130237023 | Methods Of Forming A Vertical Transistor And At Least A Conductive Line Electrically Coupled Therewith - Trenches are formed into semiconductive material. Masking material is formed laterally over at least elevationally inner sidewall portions of the trenches. Conductivity modifying impurity is implanted through bases of the trenches into semiconductive material there-below. Such impurity is diffused into the masking material received laterally over the elevationally inner sidewall portions of the trenches and into semiconductive material received between the trenches below a mid-channel portion. An elevationally inner source/drain is formed in the semiconductive material below the mid-channel portion. The inner source/drain portion includes said semiconductive material between the trenches which has the impurity therein. A conductive line is formed laterally over and electrically coupled to at least one of opposing sides of the inner source/drain. A gate is formed elevationally outward of and spaced from the conductive line and laterally adjacent the mid-channel portion. Other embodiments are disclosed. | 09-12-2013 |
20140073100 | Methods Of Forming A Vertical Transistor, Methods Of Forming Memory Cells, And Methods Of Forming Arrays Of Memory Cells - Trenches are formed into semiconductive material. Masking material is formed laterally over at least elevationally inner sidewall portions of the trenches. Conductivity modifying impurity is implanted through bases of the trenches into semiconductive material there-below. Such impurity is diffused into the masking material received laterally over the elevationally inner sidewall portions of the trenches and into semiconductive material received between the trenches below a mid-channel portion. An elevationally inner source/drain is formed in the semiconductive material below the mid-channel portion. The inner source/drain portion includes said semiconductive material between the trenches which has the impurity therein. A conductive line is formed laterally over and electrically coupled to at least one of opposing sides of the inner source/drain. A gate is formed elevationally outward of and spaced from the conductive line and laterally adjacent the mid-channel portion. Other embodiments are disclosed. | 03-13-2014 |
20140315364 | Methods Of Forming A Vertical Transistor - Trenches are formed into semiconductive material. Masking material is formed laterally over at least elevationally inner sidewall portions of the trenches. Conductivity modifying impurity is implanted through bases of the trenches into semiconductive material there-below. Such impurity is diffused into the masking material received laterally over the elevationally inner sidewall portions of the trenches and into semiconductive material received between the trenches below a mid-channel portion. An elevationally inner source/drain is formed in the semiconductive material below the mid-channel portion. The inner source/drain portion includes said semiconductive material between the trenches which has the impurity therein. A conductive line is formed laterally over and electrically coupled to at least one of opposing sides of the inner source/drain. A gate is formed elevationally outward of and spaced from the conductive line and laterally adjacent the mid-channel portion. Other embodiments are disclosed. | 10-23-2014 |
Patent application number | Description | Published |
20110084841 | METHOD AND APPARATUS FOR DETERMINING RANGE INFORMATION OF A NODE IN A WIRELESS SYSTEM - A method and apparatus for determining a range within a wireless communication system is provided herein. The range information can then be used to locate a node (e.g., an asset tag). During operation, the minimum transmission power of a source transceiver (e.g., an RFID reader) that enables a tag to be detected will be used to indicate distance. Changes in transmit power will be used to indicate relative changes in distance to a particular node. The reader will be configured to always operate at a transmission power that will result in a certain percentage (e.g., 50%) detection rate for a target transceiver (e.g., an RFID asset tag). As the reader moves closer to the tag, the minimum detection power will decrease; as it moves farther from the tag, the minimum detection power will increase. This information is displayed to give a general change in range information between the RFID reader and the asset tag (e.g., increasing range or decreasing range). An individual will be able to easily locate the asset tag by using the displayed information. | 04-14-2011 |
20110147455 | ORIENTING A SCANNING DEVICE WITH RESPECT TO A TARGET LOCATION - Disclosed is a method for a scanning device to tell its user how to best orient the scanning device to scan a target location. The user approaches the target location and initiates a scan. The results of the scan are analyzed and compared to information about the target location. Based on the analysis, the user is told how to re-orient the scanning device, if that is necessary to achieve an acceptable re-scan of the target location. In a preferred embodiment, a screen on the scanning device presents a two-dimensional map based on the scan results and on the known relative locations of the target location and of nearby non-target locations. Locations on the map are highlighted to tell the user the results of the scan and to direct him to re-orient the scanning device if necessary. | 06-23-2011 |
20110260922 | MAPPING LOCATIONS BASED ON RECEIVED SIGNAL STRENGTHS - Disclosed is a system for updating an RSSI-based map. A scanning devices notes which tags are seen during a scan and measures a “proxy distance” from the scanning device to each tag. When the scan is initiated, the scanning device measures the RSSIs from the local WAPs. The current location of the scanning device is determined by triangulating from the proxy distances of the scanned tags. That location is then correlated with the contemporaneously measured RSSIs. The correlation is used to update the RSSI-based map. In some embodiments, it is not the scanning device that measures the RSSIs. Instead, the WAPs measure the RSSIs from the scanning device whenever the scanning device transmits the results of a scan. In some embodiments, the operator of the mapped environment places scannable tags at fixed locations. Scans of these fixed-location tags are especially useful when determining the current location of the scanning device. | 10-27-2011 |