| Patent application number | Description | Published |
|---|
| 20090050983 | SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING THE SAME - There is provided a trap memory device suppresses electric charges from flowing from the outside into a charge accumulation region and accumulated electric charges from diffusing to the outside or flowing out due to a defect. A gate conductor | 02-26-2009 |
| 20090115002 | Semiconductor Device - There is provided a semiconductor device including: a first field effect transistor region including a gate insulating film, a gate electrode and gate sidewalls formed in a P channel forming region; and a second field effect transistor region including a gate insulating film, a gate electrode and gate sidewalls formed in an N channel forming region on a semiconductor substrate, wherein in the first and second field effect transistor regions, the gate electrodes are composed primarily of a silicide of metal M represented as M(x)Si(1−x)(0| 05-07-2009 | |
| 20090201739 | METHOD FOR DRIVING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE - In a case of writing to a trap type non-volatile memory cell that includes: a laminated insulating film, containing a charge accumulation layer, that is formed on a semiconductor substrate where source, drain and well regions are formed; and a first gate electrode formed on the laminated insulating film, charge injections that are carried on a single memory node multiple times under two or more different writing conditions, the writing condition is a combination of a well voltage applied to the well, a drain voltage applied to the drain and a gate voltage is applied to the first gate. Thereby, it is possible to form a trapezoid-shaped electron distribution in the charge accumulation layer, and thus prevent the charge retention characteristic from deteriorating. | 08-13-2009 |
| 20090316484 | SEMICONDUCTOR MEMORY DEVICE, METHOD OF DRIVING THE SAME AND METHOD OF MANUFACTURING THE SAME - Disclosed is a semiconductor storage device comprising a semiconductor substrate, a first and a second impurity diffusion layer formed in the semiconductor substrate, a gate insulating film formed on the semiconductor substrate, and a first gate electrode formed on the semiconductor substrate via the gate insulating film. The gate insulating film has a nitrogen-containing silicon oxide film inside, and a silicon oxide film is so arranged on both sides of the nitrogen-containing silicon oxide film as to sandwich the nitrogen-containing silicon oxide film. In addition, the nitrogen composition in the nitrogen-containing silicon oxide film is increased from the semiconductor substrate side to the first gate electrode side. | 12-24-2009 |
| 20100025753 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device including: source-drain regions formed on a silicon substrate with a channel forming region sandwiched therebetween; a word gate electrode formed on the channel forming region via a word gate insulating film not including a charge storage layer; a control gate formed on the silicon substrate on one side of the word gate electrode via a trap insulating film including a charge storage layer; and a control gate formed on the silicon substrate on the other side of the word gate electrode via a trap insulating film including a charge storage layer. A bottom of the word gate electrode is made to be higher than the control gate and a bottom of the control gate, and a level difference between the bottoms of the electrodes is made to be larger than a physical film thickness of the word gate insulating film. | 02-04-2010 |
| 20100025755 | SEMICONDUCTOR DEVICE - In the trap type memory chip the withstanding voltage is raised up, and then the electric current for reading out is increased. There are formed on the p-type semiconductor substrate | 02-04-2010 |
| 20100090257 | SEMICONDUCTOR DEVICE, AND ITS MANUFACTURING METHOD - A channel is formed at a recessed portion or a projecting portion of a substrate, and a gate insulating film is formed so as to have first to third insulating regions along the channel. Each of the gate insulating films of the first and third insulating regions has a first gate insulating film containing no electric charge trap formed on a plane different from a principal surface of the substrate, an electric charge accumulating film containing an electric charge trap, and a second gate insulating film containing no electric charge trap. The gate insulating film of the second insulating region at the middle is formed on a plane parallel to the principal surface of the substrate and is composed of only a third gate insulating film containing no electric charge trap. | 04-15-2010 |
| 20110096595 | SEMICONDUCTOR MEMORY DEVICE AND OPERATION METHOD THEREOF - Disclosed is a resistance change type nonvolatile memory that has an insulation film structure, is advantageous for the implementation of high integration, and achieves a stable switching characteristic, and a manufacturing method therefor. The memory includes at least an MIM (Metal/Insulator/Metal) structure including an insulation film ( | 04-28-2011 |
| 20110157959 | SEMICONDUCTOR STORAGE DEVICE, MEMORY CELL ARRAY, AND A FABRICATION METHOD AND DRIVE METHOD OF A SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device is provided for solving the problem of the inability to simultaneously realize high reliability and decreased cell area. A selection electrode ( | 06-30-2011 |
| 20120267598 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes at least first and second electrodes, and a layer including a transition metal oxide layer sandwiched between the first and second electrodes. The transition metal oxide layer includes first and second transition metal oxide layers formed of different first and second transition metals, respectively. The first transition metal oxide layer is provided on the first electrode side, the second transition metal oxide layer is provided on the second electrode side, the first transition metal oxide layer and the second transition metal oxide layer are in contact with each other, the first transition metal oxide layer has an oxygen concentration gradient from the interface between the first transition metal oxide layer and the second transition metal oxide layer toward the first electrode side, and the oxygen concentration at the interface is greater than the oxygen concentration on the first electrode side. | 10-25-2012 |
| 20120286347 | Semiconductor device - In the trap type memory chip the withstanding voltage is raised up, and then the electric current for reading out is increased. There are formed on the p-type semiconductor substrate | 11-15-2012 |
