Patent application number | Description | Published |
20100295178 | SEMICONDUCTOR CHIP PACKAGE AND MANUFACTURING METHOD THEREOF - A first wiring pattern is formed on a surface of a first support plate; a semiconductor chip is disposed on the first wiring pattern; and electrode terminals of the semiconductor chip are electrically connected to the first wiring pattern at required positions. Post electrodes connected to a second wiring pattern of a wiring-added post electrode component integrally connected by a second support plate are collectively fixed and electrically connected to the first wiring pattern formed on the first support plate at predetermined positions. After sealing with resin, the first and second support plates are separated; a glass substrate is affixed on a front face side; and external electrodes connected to the second wiring pattern are formed on a back face side. | 11-25-2010 |
20110001235 | STACKED SEMICONDUCTOR DEVICE AND FABRICATION METHOD FOR SAME - A stacked semiconductor device is constructed by stacking in two levels: a lower semiconductor device having a wiring board, at least one semiconductor chip mounted on a first surface of the wiring board and having electrodes electrically connected to wiring by way of a connection means, an encapsulant composed of insulating plastic that covers the semiconductor chip and the connection means, a plurality of electrodes formed overlying the wiring of a second surface of the wiring board, and a plurality of linking interconnects each having a portion connected to the wiring of the first surface of the wiring board and another portion exposed on the surface of the encapsulant; and an upper semiconductor device in which each electrode overlies and is electrically connected to the exposed portions of each of the linking interconnects of the lower semiconductor device. The linking interconnects extend from the first surface of the wiring board to the side surfaces and upper surface of the encapsulant, and moreover, electrically connect with wiring of the wiring board that projects from the encapsulant. | 01-06-2011 |
20110057325 | CHIP-SIZE DOUBLE SIDE CONNECTION PACKAGE AND METHOD FOR MANUFACTURING THE SAME - A low resistance metal is charged into holes formed in a semiconductor substrate to thereby form through electrodes. Post electrodes of a wiring-added post electrode component connected together by a support portion thereof are simultaneously fixed to and electrically connected to connection regions formed on an LSI chip. On the front face side, after resin sealing, the support portion is separated so as to expose front face wiring traces. On the back face side, the semiconductor substrate is grounded so as to expose tip ends of the through electrodes. The front face wiring traces exposed to the front face side and the tip ends of the through electrodes exposed to the back face side are used as wiring for external connection. | 03-10-2011 |
20110062584 | THREE-DIMENSIONALLY INTEGRATED SEMICONDUTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A wiring substrate has, on each of opposite faces thereof, connection pad portions to which various circuit elements are connected, and wiring traces for connecting the connection pad portions. The wiring substrate also has a through wiring portion for establishing mutual connection between the connection pad portions and the wiring traces on the front face and those on the back face. A post electrode component is formed such that it includes a plurality of post electrodes supported by a support portion. A semiconductor chip is attached to the back face of the wiring substrate, and is connected to the connection pad portions on the back face. After the post electrode component is fixed to and electrically connected to the wiring traces at predetermined positions, and resin sealing is performed, the support portion is separated so as to expose end surfaces of the post electrodes or back face wiring traces connected thereto. Another circuit element is disposed on the front face of the wiring substrate, and is connected to the connection pad portions on the front face. | 03-17-2011 |
20110089551 | SEMICONDUCTOR DEVICE WITH DOUBLE-SIDED ELECTRODE STRUCTURE AND ITS MANUFACTURING METHOD - According to the present invention, a recess portion is formed in a package substrate which is formed of a multilayer organic substrate having a multilayer wiring, and an LSI chip is accommodated within the recess portion. Wiring traces are formed on the upper surface of a resin which seals the LSI chip connected to the multilayer wiring. The wiring traces are connected to terminal wiring traces connected to the multilayer wiring on the front face of the package substrate and to front-face bump electrodes for external connection on the upper surface of the resin. On the back face side of the package substrate, back-face bump electrodes for external connection are formed and connected to the multilayer wiring. | 04-21-2011 |
20120127667 | HEAT SINK PACKAGE AND METHOD OF MANUFACTURING - A circuit element is arranged on an organic substrate and connected to a wiring pattern arranged on the organic substrate. An internal connection electrode is formed on a conductive support body by electroforming so as to obtain a unitary block of the internal connection electrode and the support body. Each end of each of the internal connection electrodes connected into a unitary block by the support body is connected to the wiring pattern. After the circuit element is sealed by resin, the support body is peeled off, so as to obtain individual internal connection electrodes separately and the other end of each of the internal connection electrodes is used as an external connection electrode on the front surface while the external connection electrode on the rear surface is connected to the wiring pattern. | 05-24-2012 |
20120164790 | DOUBLE-FACED ELECTRODE PACKAGE, AND ITS MANUFACTURING METHOD - A dual-face package has an LSI chip sealed with a mold resin, and electrodes for external connections on both of the front face and the back face. The LSI chip is bonded onto the die pad of a leadframe whose outer lead portions are exposed as back-face electrodes at at least the back face. The LSI chip and a plurality of inner lead portions of the leadframe are connected by wiring. At least some of the plurality of inner lead portions have front-face electrodes integrally formed by working a portion of the leadframe. Head faces of the front-face electrodes, or bump electrodes connected to the respective head faces of the front-face electrodes serve as electrodes for external connections to another substrate, element, or the like. | 06-28-2012 |
20120261169 | INTERCONNECT-USE ELECTRONIC COMPONENT AND METHOD FOR PRODUCING SAME - The present invention enables additional processes required for forming vertical wiring and rewiring in a double face package (DFP) or a wafer level chip size package (WLCSP) to be implemented through use of a component for vertical wiring and rewiring, to thereby simplify the manufacturing process and reduce cost. An electronic component for interconnection is incorporated into an electronic device package in which a circuit element including a semiconductor chip is disposed and which has external electrodes connected to the circuit element via vertical interconnects and horizontal interconnects. This electronic component for interconnection is composed of a wiring substrate which includes horizontal interconnects and vertical interconnects connected to the horizontal interconnects and extending therefrom in a vertical direction; and a support plate to which the wiring substrate having the horizontal interconnects and the vertical interconnects is bonded through use of an adhesive which can be separated with water. | 10-18-2012 |
20140327024 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD FOR SAME - A semiconductor device includes an electrical insulating layer with superior heat resistance, heat dissipation, and durability, and which is manufactured through a process with good cost performance and process performance. In a semiconductor device including a first substrate to which a semiconductor chip is mounted directly or indirectly, and a white insulating layer formed on a surface of the first substrate and functioning as a reflecting material, the semiconductor chip is an LED, at least the surface of the first substrate is made of a metal, and a stacked structure of the white insulating layer and a metal layer is formed by coating a liquid material, which contains SiO | 11-06-2014 |
Patent application number | Description | Published |
20080223196 | Semiconductor Device Having Music Generation Function, and Mobile Electronic Device, Mobile Telephone Device, Spectacle Instrument, and Spectacle instrument Set Using the Same - There is provided a semiconductor device having a music generation function for automatically generating music data from image data inputted without preparing music information in advance, and a mobile electronic device, a mobile telephone device, a spectacle instrument, and a spectacle instrument set using the same. The device includes a miniature camera | 09-18-2008 |
20080265430 | Semiconductor Device an Process for Fabricating the Same - A thin stacked semiconductor device has a plurality of circuits that are laminated and formed sequentially in a specified pattern to form a multilayer wiring part. At the stage for forming the multilayer wiring part, a filling electrode is formed on the semiconductor substrate such that the surface is covered with an insulating film, a post electrode is formed on specified wiring at the multilayer wiring part, a first insulating layer is formed on one surface of the semiconductor substrate, the surface of the first insulating layer is removed by a specified thickness to expose the post electrode, and the other surface of the semiconductor substrate is ground to expose the filling electrode and to form a through-type electrode, A second insulating layer is formed on one surface of the semiconductor substrate while exposing the forward end of the through-type electrode, and bump electrodes are formed on both electrodes. | 10-30-2008 |
20090050994 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE WITH ELECTRODE FOR EXTERNAL CONNECTION AND SEMICONDUCTOR DEVICE OBTAINED BY MEANS OF SAID METHOD - A circuit element is disposed on an organic substrate and is connected to a wiring pattern provided on the organic substrate. Internal connection electrodes are formed on a support of a conductive material through electrofomiing such that the internal connection electrodes are integrally connected to the support. First ends of the internal connection electrodes integrally connected by the support are connected to the wiring pattern. After the circuit element is resin-sealed, the support is removed so as to separate the internal connection electrodes from one another. Second ends of the internal connection electrodes are used as external connection electrodes on the front face, and external connection electrodes on the back face are connected to the wiring pattern. | 02-26-2009 |
20090072381 | SEMICONDUCTOR DEVICE WITH DOUBLE-SIDED ELECTRODE STRUCTURE AND ITS MANUFACTURING METHOD - According to the present invention, a recess portion is formed in a package substrate which is formed of a multilayer organic substrate having a multilayer wiring, and an LSI chip is accommodated within the recess portion. Wiring traces are formed on the upper surface of a resin which seals the LSI chip connected to the multilayer wiring. The wiring traces are connected to terminal wiring traces connected to the multilayer wiring on the front face of the package substrate and to front-face bump electrodes for external connection on the upper surface of the resin. On the back face side of the package substrate, back-face bump electrodes for external connection are formed and connected to the multilayer wiring. | 03-19-2009 |
20090140364 | PACKAGED SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The present invention connects a first wiring portion located at one side of a substrate and a second wiring portion located at the other side. A side electrode connected to the first wiring portion is formed, and the second wiring portion is formed on an insulating layer formed on the substrate. An exposed end of the second wiring portion formed when singulated into individual semiconductor package and the side electrode are wired by ink jet system using nano metal particles. Particularly, when copper is used, the wiring by the ink jet system is performed by the reduction of a metal surface oxidation film and/or removal of organic matters by atomic hydrogen. | 06-04-2009 |
20110201178 | SEMICONDUCTOR DEVICE AND PROCESS FOR FABRICATING THE SAME - A thin stacked semiconductor device has a plurality of circuits that are laminated and formed sequentially in a specified pattern to form a multilayer wiring part. At the stage for forming the multilayer wiring part, a filling electrode is formed on the semiconductor substrate such that the surface is covered with an insulating film, a post electrode is formed on specified wiring at the multilayer wiring part, a first insulating layer is formed on one surface of the semiconductor substrate, the surface of the first insulating layer is removed by a specified thickness to expose the post electrode, and the other surface of the semiconductor substrate is ground to expose the filling electrode and to form a through-type electrode. A second insulating layer if formed on one surface of the semiconductor substrate while exposing the forward end of the through-type electrode, and bump electrodes are formed on both electrodes. | 08-18-2011 |
20140091459 | Chip-size, double side connection package and method for manufacturing the same - A low resistance metal is charged into holes formed in a semiconductor substrate to thereby form through electrodes. Post electrodes of a wiring-added post electrode component connected together by a support portion thereof are simultaneously fixed to and electrically connected to connection regions formed on an LSI chip. On the front face side, after resin sealing, the support portion is separated so as to expose front face wiring traces. On the back face side, the semiconductor substrate is grounded so as to expose tip ends of the through electrodes. The front face wiring traces exposed to the front face side and the tip ends of the through electrodes exposed to the back face side are used as wiring for external connection. | 04-03-2014 |
20140131891 | SEMICONDUCTOR DEVICE AND PROCESS FOR FABRICATING THE SAME - A thin stacked semiconductor device has a plurality of circuits that are laminated and formed sequentially in a specified pattern to form a multilayer wiring part. At the stage for forming the multilayer wiring part, a filling electrode is formed on the semiconductor substrate such that the surface is covered with an insulating film, a post electrode is formed on specified wiring at the multilayer wiring part, a first insulating layer is formed on one surface of the semiconductor substrate, the surface of the first insulating layer is removed by a specified thickness to expose the post electrode, and the other surface of the semiconductor substrate is ground to expose the filling electrode and to form a through-type electrode. A second insulating layer if formed on one surface of the semiconductor substrate while exposing the forward end of the through-type electrode, and bump electrodes are formed on both electrodes. | 05-15-2014 |