Patent application number | Description | Published |
20080201099 | PULSE WIDTH ADJUSTMENT CIRCUIT, PULSE WIDTH ADJUSTMENT METHOD, AND TEST APPARATUS FOR SEMICONDUCTOR DEVICE - A semiconductor test apparatus to test a semiconductor circuit includes a pattern generator which generates a test pattern for testing the semiconductor circuit, a waveform shaper which shapes a test signal to be supplied to the semiconductor circuit based on the test pattern, a pulse width adjusting circuit which generates a timing signal for determining a phase of the test signal by adjusting a pulse width of an input pulse signal and outputs the timing signal to the waveform shaper, and a judging section which judges whether the semiconductor circuit is good or bad based on an output signal output from the semiconductor circuit. The pulse width adjusting circuit includes a first delay circuit which outputs a first delay signal generated by delaying the pulse signal by a certain delay time, a second delay circuit which outputs a second delay signal generated by delaying the pulse signal by a different delay time from the first delay circuit, and an output section which, in accordance with the first and second delay signals, generates and outputs the timing signal having a pulse width corresponding to a difference between the delay times respectively achieved by the first and second delay circuits. | 08-21-2008 |
20080258714 | Delay circuit and test apparatus - There is provided a delay circuit that delays an input signal to output the delayed signal. The delay circuit includes a first delay element operable to receive the input signal and delay the input signal to output the delayed signal, a buffer operable to receive the delay signal output from the first delay element and correct a dullness of a waveform of the delay signal generated from the first delay element to output the corrected signal, and a second delay element operable to receive the delay signal output from the buffer and delay the delay signal to output the delayed signal. | 10-23-2008 |
20090039939 | VARIABLE DELAY CIRCUIT, TESTING APPARATUS, AND ELECTRONIC DEVICE - Provided is a variable delay circuit outputting an output signal delayed with respect to an input signal by a designated delay time, including: a delay controller outputting a control voltage according to the delay time; a MOS transistor receiving the control voltage at a gate, and outputs a drain current according to the control voltage; a correction section connected in parallel to a source and a drain of the current controlling MOS transistor, and outputs a correction current on a monotonic decrease as the drain current increases in a range larger than a predetermined boundary current within a normal usage range of the drain current; and a delay element running an output current resulting from adding the correction current to the drain current, between the delay element and an output terminal of the variable delay circuit, in changing a signal value of the output signal according to the input signal. | 02-12-2009 |
20090058452 | TEST APPARATUS AND TEST METHOD - Provided is a test apparatus that tests fluctuation of a power supply voltage supplied to a device under test, including an oscillator that outputs a clock signal having a frequency that corresponds to the power supply voltage supplied to the power supply input terminal of the device under test, and a measuring section that measures the frequency of the clock signal. For example, the oscillator outputs as the clock signal an output signal of any one negative logic element from among an odd number of negative logic elements connected in a loop, and at least one of the negative logic elements operates using, as a voltage source, a voltage corresponding to the power supply voltage supplied to the power supply input terminal of the device under test. | 03-05-2009 |
20090132884 | TIMING GENERATOR AND SEMICONDUCTOR TESTING APPARATUS - A timing generator that needs no analog circuit for adding jitters and allows the circuit scale and power consumption to be reduced. There are included a counter for performing a counting operation synchronized with a reference clock signal: a timing memory for outputting respective data corresponding to the quotient and remainder resulting from dividing the time from the front of a basic period until a generation of a timing edge by the period of the reference clock signal: a coincidence detecting circuit for outputting a signal that exhibits a high level when the count value of the counter coincides with the quotient: a jitter generating circuit for outputting as a jitter amplitude value: adders for adding a time corresponding to the remainder and a time represented by the jitter amplitude value outputted from the jitter generating circuit: and a variable delay circuit for delaying the output signal from the coincidence detecting circuit by the time represented by the addition result of the adders and outputting the delayed output signal. | 05-21-2009 |
20090146703 | OSCILLATION CIRCUIT, TEST APPARATUS AND ELECTRONIC DEVICE - Provided is an oscillation circuit for generating an oscillation signal synchronized with a supplied reference clock, including: a voltage control oscillation section that, when triggered by each edge of the reference clock, stops oscillation of the oscillation signal having a frequency in accordance with a supplied control voltage to start new oscillation; a phase comparing section that compares a phase of a comparison signal that is in accordance with the oscillation signal outputted from the voltage control oscillation section and a phase of a signal that is in accordance with the reference clock; and a voltage control section that supplies the control voltage in accordance with a comparison result of the phase comparing section, to the voltage control oscillation section. | 06-11-2009 |
20090160536 | ELECTRONIC DEVICE, LOAD FLUCTUATION COMPENSATION CIRCUIT, POWER SUPPLY, AND TEST APPARATUS - Provided is a load fluctuation compensation circuit, including a first delay circuitry section that delays a clock signal supplied thereto by a delay amount that fluctuates by a prescribed first fluctuation amount in relation to a unit fluctuation amount of a power supply voltage supplied to a performance circuit; a second delay circuitry section that is disposed in parallel with the first delay circuitry section and that delays the clock signal supplied thereto by a delay amount that fluctuates by a second fluctuation amount, which is greater than the first fluctuation amount, in relation to the unit fluctuation amount of the power supply voltage supplied to the performance circuit; a load circuit that is connected to a common power supply wiring in parallel with the performance circuit; and a phase detecting section that detects a phase difference between the clock signal output by the first delay circuitry section and the clock signal output by the second delay circuitry section and that controls an amount of current consumed by the load circuit based on the detected phase difference. | 06-25-2009 |
20090184741 | Delay lock loop circuit, phase lock loop circuit, timing generator, semiconductor tester and semiconductor integrated circuit - A delay lock loop circuit and a phase lock loop circuit are designed to reduce a lock-up time, extend a lock range without increasing the number of bits of a counter, and quickly return to a lock target upon deviation from the lock target. There are provided with a plurality of phase comparators | 07-23-2009 |
20090256577 | Delay Lock Loop Circuit, Timing Generator, Semiconductor Test Device, Semiconductor Integrated Circuit, and Delay Amount Calibration Method - A method replaces a delay amount measurement in which an initially set value of a counter is determined by a technique which replaces measurement of a delay amount, whereby a time required for calibration of a delay circuit can be reduced. One counter set value of a plurality of counter set values is loaded, a delay lock loop circuit is switched to a lock mode, and a sequence circuit of a cycle slip detection circuit is reset. Thereafter, a cycle slip detection signal output from the sequence circuit is read, and on the basis of this cycle slip detection signal, it is judged whether or not an output signal of a delay circuit causes cycle slip. If the cycle slip is caused, the counter set value is switched. On the other hand, if any cycle slip is not caused, the counter set value is locked, thereby terminating the process. | 10-15-2009 |
20090273384 | VERNIER DELAY CIRCUIT - A ring oscillator oscillates at a frequency determined by an input bias signal. A bias signal adjusting unit produces a bias signal for the ring oscillator using feedback so that the oscillation frequency of the ring oscillator matches a predetermined reference frequency. An individual bias circuit includes a plurality of bias circuits provided for a total of N second variable delay elements, respectively. The bias circuits are configured such that the bias signals can be individually adjusted. | 11-05-2009 |
20090287431 | TEST APPARATUS, TEST METHOD AND COMPUTER READABLE MEDIUM - Provided is a test apparatus for testing a device under test, the test apparatus including: a pattern generating section that inputs a test pattern to the device under test; a judging section that judges whether the device under test is defective or not, based on an output signal outputted from the device under test; a power supply apparatus that supplies a source power to the device under test; and a setting section that detects a fluctuation amount of the source voltage resulting when the test pattern is inputted to the device under test, and sets, based on the detected fluctuation amount, a current range within which a compensation current that is in accordance with a fluctuation of a consumption current consumed by the device under test is generated at a predetermined number of levels so as to compensate a fluctuation of a source voltage to be applied to the device under test attributable to the fluctuation of the consumption current. | 11-19-2009 |
20100019795 | VARIABLE DELAY CIRCUIT, TIMING GENERATOR AND SEMICONDUCTOR TESTING APPARATUS - The accuracy of the delay amount to be imparted to a timing signal is improved by increasing the delay amount obtained by a first stage of a delay element. | 01-28-2010 |
20110089983 | LOOP TYPE CLOCK ADJUSTMENT CIRCUIT AND TEST DEVICE - A variable delay circuit applies a variable delay that corresponds to an analog signal to a reference clock so as to generate a delayed clock. A phase detection unit detects the phase difference between the delayed clock and the reference clock, and generates a phase difference signal having a level that corresponds to the phase difference. A counter performs a counting up operation or a counting down operation according to the level of the phase difference signal. A digital/analog converter converts the count value of the counter into an analog signal, and supplies the count value thus converted to the variable delay circuit. The counter comprises: a first counter configured to use a first thermometer code to count the lower group of digits of the count value according to the phase difference signal; a second counter configured to use a second thermometer code to count an upper group of digits of the count value according to the phase difference signal; and a control circuit configured to perform a control operation such that the Hamming distance is maintained at 1 even in a carry operation and a borrow operation of the first counter and the second counter. | 04-21-2011 |
20110109377 | SEMICONDUCTOR INTEGRATED CIRCUIT - A circuit block operates while receiving a clock from an external circuit. A load balance circuit is connected to a shared power supply terminal together with the circuit block, and provides predetermined power consumption. A clock detection unit detects input of the clock from an external circuit. When the clock detection unit detects stopping of input of the clock, the load balance circuit is switched to the active state. | 05-12-2011 |
20110128052 | CLOCK HAND-OFF CIRCUIT - A second latch latches the output data of a first latch using a third clock having the same frequency as that of a first clock. A third latch latches the output data of the second latch using a second clock having a frequency N (N represents an integer) times that of the first clock and the third clock. The second clock and the third clock have a frequency division/multiplication relation therebetween. | 06-02-2011 |