Patent application number | Description | Published |
20100013006 | SEMICONDUCTOR DEVICE - A semiconductor device has a semiconductor substrate having a surface layer and a p-type semiconductor region, wherein the surface layer includes a contact region, a channel region and a drift region, the channel region is adjacent to and in contact with the contact region, the drift region is adjacent to and in contact with the channel region and includes n-type impurities at least in part, and the p-type semiconductor region is in contact with the drift region and at least a portion of a rear surface of the channel region, a main electrode disposed on the surface layer and electrically connected to the contact region, a gate electrode disposed on the surface layer and extending from above a portion of the contact region to above at least a portion of the drift region via above the channel region, and an insulating layer covering at least the portion of the contact region and not covering at least the portion of the drift region. The gate electrode and the contact region are insulated by the insulating layer, and the gate electrode and the drift region are in direct contact to form a Schottky junction. | 01-21-2010 |
20100038681 | TRANSISTOR - An HEMT type transistor is disclosed that is a normally off type, and in which variations in the gate threshold voltage are small. A transistor is provided with a p-type region, a barrier region, an insulation film, a gate electrode. The channel region is connected to an upper surface of the p-type region. The channel region is n-type or i-type and provided with a first channel region and a second channel region. The barrier region is forming a hetero-junction with an upper surface of the first channel region. The insulation film is connected to an upper surface of the second channel region and an upper surface of the barrier region. The gate electrode faces the second channel region and the barrier region via the insulation film. The first channel region and the second channel region are arranged in series in a current pathway. | 02-18-2010 |
20100044753 | SEMICONDUCTOR DEVICE - A nitride semiconductor device | 02-25-2010 |
20100295098 | III-V HEMT DEVICES - A semiconductor device has a stacked structure in which a p-GaN layer, an SI-GaN layer, and an AlGaN layer are stacked, and has a gate electrode that is formed at a top surface side of the AlGaN layer. A band gap of the AlGaN layer is wider than a band gap of the p-GaN layer and the SI-GaN layer. Moreover, impurity concentration of the SI-GaN layer is less than 1×10 | 11-25-2010 |
20110316049 | NITRIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided are a vertical nitride semiconductor device in which occurrence of leak currents can be suppressed, and a method for manufacturing such nitride semiconductor device. A nitride semiconductor device, which is a vertical HEMT, is provided with an n | 12-29-2011 |
20120132927 | OHMIC ELECTRODE AND METHOD OF FORMING THE SAME - An ohmic electrode for a p-type SiC semiconductor, and a method of forming the ohmic electrode. The ohmic electrode has an ohmic electrode layer, which has an amorphous structure and which is made of a Ti | 05-31-2012 |
20120217639 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A manufacturing method of a semiconductor device including an electrode having low contact resistivity to a nitride semiconductor is provided. The manufacturing method includes a carbon containing layer forming step of forming a carbon containing layer containing carbon on a nitride semiconductor layer, and a titanium containing layer forming step of forming a titanium containing layer containing titanium on the carbon containing layer. A complete solid solution Ti (C, N) layer of TiN and TiC is formed between the titanium containing layer and the nitride semiconductor layer. As a result, the titanium containing layer comes to be in ohmic contact with the nitride semiconductor layer throughout the border therebetween. | 08-30-2012 |
20140175518 | III-V HEMT DEVICES - A semiconductor device has a stacked structure in which a p-GaN layer, an SI-GaN layer, and an AlGaN layer are stacked, and has a gate electrode that is formed at a top surface side of the AlGaN layer. A band gap of the AlGaN layer is wider than a band gap of the p-GaN layer and the SI-GaN layer. Moreover, impurity concentration of the SI-GaN layer is less than 1×10 | 06-26-2014 |
20140231827 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A method of manufacturing a semiconductor device includes forming an ohmic electrode in a first area on one of main surfaces of a silicon carbide layer, siliciding the ohmic electrode, and forming a Schottky electrode in a second area on the one of the main surfaces of the silicon carbide layer with self alignment. The second area is exposed where the ohmic electrode is not formed. | 08-21-2014 |
20140319540 | SEMICONDUCTOR DEVICE - A semiconductor device is provided with a semiconductor substrate in which a power semiconductor element part and a temperature sensing diode part are provided. The temperature sensing diode part includes a first semiconductor region, a second semiconductor region, a first base region, and a first drift region. In the semiconductor substrate, an isolation trench is formed, which passes through the first base region, extends to the first drift region, and surrounds an outer periphery of the temperature sensing diode part. At least a part of one of side walls of the isolation trench is in contact with the power semiconductor element part, and the other side wall of the isolation trench is in contact with the temperature sensing diode part. | 10-30-2014 |
20140319577 | SEMICONDUCTOR DEVICE - A semiconductor device disclosed in this specification includes a p+ contact region, an n+ source region, a p− base region, an n− drift region, a gate electrode, an insulator, a p+ electric field alleviating layer, and a p− positive hole extraction region. The electric field alleviating layer has same impurity concentration as the base region or higher, contacts a lower surface of the base region, and is formed in a same depth as the gate trench or in a position deeper than the gate trench. A positive hole extraction region extends to contact the electric field alleviating layer from a position to contact an upper surface of a semiconductor substrate or a first semiconductor region, and extracts a positive hole that is produced in the electric field alleviating layer at the avalanche breakdown to the upper surface of the semiconductor substrate. | 10-30-2014 |
20140339569 | SEMICONDUCTOR DEVICE - A semiconductor device formed on a silicon carbide substrate that has a front surface on which an electrode is provided and a back surface on which an electrode is provided includes a drain layer, a drift layer, a base layer, a gate electrode that is located in a trench that extends from the front surface into the drift layer and is insulated by an insulating film, a some layer, a buried layer that is provided between the drift layer and the base layer and is formed such that the depth from the front surface to an end thereof on the side of the drift layer is greater than the depth from the front surface to a distal end of the trench, and a first epitaxial layer that is provided between the buried layer and the base layer and has a higher impurity concentration than the buried layer. | 11-20-2014 |