Patent application number | Description | Published |
20090267123 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a semiconductor substrate; a plurality of transistors on the semiconductor substrate, each of the transistors has a source and drain region; an interlayer insulating film on the semiconductor substrate and the plurality of transistors; and at least three capacitors on the interlayer insulation film, each of them has a top electrode, a bottom electrode and an insulating film interposed therebetween; wherein the 1st and 2nd capacitors have an shared electrode, with the top electrodes of the 1st and 2nd capacitors, which has a 1st longer direction, the 2nd and 3rd capacitors have an shared electrode, with the bottom electrodes of the 2nd and 3rd capacitors, which has a 2nd longer direction different from the 1st direction. | 10-29-2009 |
20090283737 | NONVOLATILE STORAGE DEVICE AND METHOD FOR MANUFACTURING SAME - A nonvolatile storage device having a plurality of unit memory layers, and a plurality of layer selection transistors is provided. The plurality of unit memory layers are laminated in a direction perpendicular to a layer surface of the unit memory layers. Each of the unit memory layers includes a plurality of first wirings, a plurality of second wirings provided non-parallel to the plurality of first wirings, and a recording layer provided between the plurality of first wirings and the plurality of second wirings. The plurality of layer selection transistors are connected to at least one of the plurality of first wirings and the plurality of second wirings of each of the unit memory layers, and collectively selects the at least one in the same plane. | 11-19-2009 |
20090283739 | NONVOLATILE STORAGE DEVICE AND METHOD FOR MANUFACTURING SAME - There is provided a nonvolatile storage device including a plurality of component memory layers. The plurality of component memory layers are stacked In a direction perpendicular to a layer surface. Each of the plurality of component memory layers includes a first wiring, a second wiring provided non-parallel to the first wiring and a stacked structure unit provided between the first wiring and the second wiring and including a recording layer. At least one of the first wiring and the second wiring includes a protruding portion provided on a portion opposed to the recording layer and protruding toward the recording layer side. | 11-19-2009 |
20090289251 | NONVOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - A nonvolatile memory device includes a plurality of component memory layers stacked on one another. Each of the plurality of component memory layers includes a first wiring, a second wiring provided non-parallel to the first wiring, and a stacked structure unit provided between the first wiring and the second wiring. The stacked structure unit has a memory layer and a rectifying element. The rectifying element has a Schottky junction formed on an interface between an electrode and an oxide semiconductor. The electrode includes a metal and the oxide semiconductor includes a metal. | 11-26-2009 |
20090294751 | NONVOLATILE STORAGE DEVICE AND METHOD FOR MANUFACTURING SAME - A method for manufacturing a nonvolatile storage device with a plurality of unit memory layers stacked therein is provided. Each of the unit memory layers includes: a first interconnect extending in a first direction; a second interconnect extending in a second direction; a recording unit sandwiched between the first and second interconnects and being capable of reversibly transitioning between a first state and a second state in response to a current supplied through the first and second interconnects; and a rectifying element sandwiched between the first interconnect and the recording unit and including at least one of p-type and n-type impurities. In the method, the first interconnect, the second interconnect, the recording unit, and a layer of an amorphous material including the at least one of p-type and n-type impurities used in the plurality of unit memory layers are formed at a temperature lower than a temperature at which the amorphous material is substantially crystallized. The amorphous material used in the plurality of unit memory layers is simultaneously crystallized and the impurities included in the amorphous material used in the plurality of unit memory layers are simultaneously activated. | 12-03-2009 |
20090294836 | NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR MANUFACTURING SAME - A nonvolatile semiconductor storage device includes: a plurality of stacked units juxtaposed on a major surface of a substrate, each stacked unit aligning in a first direction parallel to the major surface of the substrate; and a gate electrode aligning parallel to the major surface in a second direction non-parallel to the first direction. Each of the plurality of stacked units includes a plurality of stacked semiconductor layers via an insulating layer. The plurality of stacked units are juxtaposed so that the spacings between adjacent stacked units are alternately a first spacing and a second spacing larger than the first spacing. The second spacing is provided at a periodic interval four times a size of a half pitch F of the bit line. The gate electrode includes a protruding portion that enters into a gap of the second spacing between the stacked units. A first insulating film, a charge storage layer, and a second insulating film are provided between a side face of the semiconductor layer and the protruding portion. | 12-03-2009 |
20110027981 | NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR MANUFACTURING SAME - A nonvolatile semiconductor storage device includes: a plurality of stacked units juxtaposed on a major surface of a substrate, each stacked unit aligning in a first direction parallel to the major surface of the substrate; and a gate electrode aligning parallel to the major surface in a second direction non-parallel to the first direction. Each of the plurality of stacked units includes a plurality of stacked semiconductor layers via an insulating layer. The plurality of stacked units are juxtaposed so that the spacings between adjacent stacked units are alternately a first spacing and a second spacing larger than the first spacing. The second spacing is provided at a periodic interval four times a size of a half pitch F of the bit line. The gate electrode includes a protruding portion that enters into a gap of the second spacing between the stacked units. A first insulating film, a charge storage layer, and a second insulating film are provided between a side face of the semiconductor layer and the protruding portion. | 02-03-2011 |
20110284946 | SEMICONDUCTOR MEMORY AND METHOD FOR MANUFACTURING SAME - A semiconductor memory capable of increasing bit density by three-dimensional arrangement of cells and a method for manufacturing the same are provided. | 11-24-2011 |
20120184078 | METHOD FOR MANUFACTURING SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a method for manufacturing a semiconductor memory device, includes forming a stacked body on a substrate by alternately stacking a first insulating film and a second insulating film, making a through-hole extending in a stacking direction of the first insulating film and the second insulating film to pierce the stacked body, forming at least a portion of a blocking insulating film, a charge trap film, and a tunneling dielectric film of a MONOS on an inner surface of the through-hole, forming a channel semiconductor on the tunneling dielectric film, making a trench in the stacked body, removing the second insulating film by performing etching via the trench, and filling a conductive material into a space made by the removing of the second insulating film. | 07-19-2012 |
20130032873 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor memory device includes a stacked body, a semiconductor pillar, and a plurality of memory cells. The stacked body includes a plurality of stacked gate electrodes and inter-electrode insulating layers provided between the gate electrodes. The semiconductor pillar punches through the stacked body. The plurality of memory cells is provided in stacking direction. The memory cell includes a charge trap layer provided between the semiconductor pillar and the gate electrode via an air gap. The block insulating layer is provided between the charge trap layer and the gate electrode. Each of the plurality of memory cells is provided with a support portion configured to keep air gap distance between the charge trap layer and the semiconductor pillar. | 02-07-2013 |