Patent application number | Description | Published |
20080248621 | Integrated Non-Volatile Memory And Peripheral Circuitry Fabrication - Non-volatile memory and integrated memory and peripheral circuitry fabrication processes are provided. Sets of charge storage regions, such as NAND strings including multiple non-volatile storage elements, are formed over a semiconductor substrate using a layer of charge storage material such as a first layer of polysilicon. An intermediate dielectric layer is provided over the charge storage regions. A layer of conductive material such as a second layer of polysilicon is deposited over the substrate and etched to form the control gates for the charge storage regions and the gate regions of the select transistors for the sets of storage elements. The first layer of polysilicon is removed from a portion of the substrate, facilitating fabrication of the select transistor gate regions from only the second layer of polysilicon. Peripheral circuitry formation is also incorporated into the fabrication process to form the gate regions for devices such as high voltage and logic transistors. The gate regions of these devices can be formed from the layer forming the control gates of the memory array. | 10-09-2008 |
20080248622 | Methods Of Fabricating Non-Volatile Memory With Integrated Peripheral Circuitry And Pre-Isolation Memory Cell Formation - Non-volatile semiconductor memory devices with dual control gate memory cells and methods of forming the same using integrated peripheral circuitry formation are provided. Strips of charge storage material elongated in a row direction across the surface of a substrate with strips of tunnel dielectric material therebetween are formed. Forming the strips defines the dimension of the resulting charge storage structures in the column direction. The strips of charge storage material can include multiple layers of charge storage material to form composite charge storage structures in one embodiment. Strips of control gate material are formed between strips of charge storage material adjacent in the column direction. The strips of charge storage and control gate material are divided along their lengths in the row direction as part of forming isolation trenches and columns of active areas. After dividing the strips, the charge storage material at the peripheral circuitry region of the substrate is etched to define a gate dimension in the column direction for a peripheral transistor. Control gate interconnects can be formed to connect together rows of isolated control gates to extrinsically form word lines. | 10-09-2008 |
20080268596 | Methods Of Fabricating Non-Volatile Memory With Integrated Select And Peripheral Circuitry And Post-Isolation Memory Cell Formation - Non-volatile semiconductor memory devices with dual control gate memory cells and methods of forming the same using integrated select and peripheral circuitry formation are provided. Strips of charge storage material elongated in a column direction across the surface of a substrate with strips of tunnel dielectric material therebetween are formed. The strips of charge storage material can include multiple layers of charge storage material to form composite charge storage structures in one embodiment. After forming isolation trenches in the substrate between active areas below the strips of charge storage material, spacer-assisted patterning is used to form a pattern at the memory array region. Strips of photoresist are patterned over a portion of the pattern at the memory array. Photoresist is also applied at the peripheral circuitry region. At least a portion of the layer stack is etched using the photoresist as a mask before removing the photoresist and etching the strips of charge storage material to form the charge storage structures. | 10-30-2008 |
20080316811 | METHOD FOR OPERATING NON-VOLATILE STORAGE WITH INDIVIDUALLY CONTROLLABLE SHIELD PLATES BETWEEN STORAGE ELEMENTS - A method for controlling non-volatile storage having individually controllable shield plates between storage elements. The shield plates are formed by depositing a conductive material such as doped polysilicon between storage elements and their associated word lines, and providing contacts for the shield plates. The shield plates reduce electromagnetic coupling between floating gates of the storage elements, and can be used to optimize programming, read and erase operations. In one approach, the shield plates provide a field induced conductivity between storage elements in a NAND string during a sense operation so that source/drain implants are not needed in the substrate. In some control schemes, alternating high and low voltages are applied to the shield plates. In other control schemes, a common voltage is applied to the shield plates. | 12-25-2008 |
20080316827 | NON-VOLATILE STORAGE WITH INDIVIDUALLY CONTROLLABLE SHIELD PLATES BETWEEN STORAGE ELEMENTS - A non-volatile storage having individually controllable shield plates between storage elements. The shield plates are formed by depositing a conductive material such as doped polysilicon between storage elements and their associated word lines, and providing contacts for the shield plates. The shield plates reduce electromagnetic coupling between floating gates of the storage elements, and can be used to optimize programming, read and erase operations. In one approach, the shield plates provide a field induced conductivity between storage elements in a NAND string during a sense operation so that source/drain implants are not needed in the substrate. In some control schemes, alternating high and low voltages are applied to the shield plates. In other control schemes, a common voltage is applied to the shield plates. | 12-25-2008 |
20080318379 | METHOD FOR FABRICATING NON-VOLATILE STORAGE WITH INDIVIDUALLY CONTROLLABLE SHIELD PLATES BETWEEN STORAGE ELEMENTS - A method for fabricating non-volatile storage having individually controllable shield plates between storage elements. The shield plates are formed by depositing a conductive material such as doped polysilicon between storage elements and their associated word lines, and providing contacts for the shield plates. The shield plates reduce electromagnetic coupling between floating gates of the storage elements, and can be used to optimize programming, read and erase operations. In one approach, the shield plates provide a field induced conductivity between storage elements in a NAND string during a sense operation so that source/drain implants are not needed in the substrate. In some control schemes, alternating high and low voltages are applied to the shield plates. In other control schemes, a common voltage is applied to the shield plates. | 12-25-2008 |
20090166704 | NON-VOLATILE STORAGE WITH SUBSTRATE CUT-OUT AND PROCESS OF FABRICATING - Shallow trench isolation regions are positioned between NAND strings (or other types of non-volatile storage). These isolation regions include sections that form concave cut-out shapes in the substrate for the NAND string (or other types of non-volatile storage). The floating gates (or other charge storage devices) of the NAND strings hang over the sections of the isolation region that form the concave cut-out shape in the substrate. To manufacture such a structure, a two step etching process is used to form the isolation regions. In the first step, isotropic etching is used to remove substrate material in multiple directions, including removing substrate material underneath the floating gates. In the second step, anisotropic etching is used to create the lower part of the isolation region. | 07-02-2009 |
20090251967 | NON-VOLATILE STORAGE HAVING A CONNECTED SOURCE AND WELL - A non-volatile storage device is disclosed that includes a set of connected non-volatile storage elements formed on a well, a bit line contact positioned in the well, a source line contact positioned in the well, a bit line that is connected to the bit line contact, and a source line that is connected to the source line contact and the well. | 10-08-2009 |
20100047979 | METHOD OF REDUCING COUPLING BETWEEN FLOATING GATES IN NONVOLATILE MEMORY - A nonvolatile memory array includes floating gates that have an inverted-T shape in cross section along a plane that is perpendicular to the direction along which floating cells are connected together to form a string. Adjacent strings are isolated by shallow trench isolation structures. | 02-25-2010 |
20100074014 | DATA STATE-BASED TEMPERATURE COMPENSATION DURING SENSING IN NON-VOLATILE MEMORY - Temperature effects in a non-volatile storage device are addressed by providing a data state-dependent, and optionally temperature dependent, sense current during verify and read operations. A different sense current is provided for each data state, so that a common temperature coefficient is realized for storage elements with different data states. The temperature coefficient for higher states can be reduced to that of lower states. During sensing, a sense time can be adjusted to achieve a desired sense current when a selected storage element is in a conductive state. A fixed voltage trip point may be maintained. During the sense time, a pre-charged capacitor discharges into a selected storage element such as via a bit line and NAND string, when the selected storage element is in a conductive state. The discharge level is translated to a current which is compared to a state-dependent, and optionally temperature dependent, reference current. | 03-25-2010 |
20100074016 | DATA RETENTION OF LAST WORD LINE OF NON-VOLATILE MEMORY ARRAYS - Techniques are disclosed herein for operating non-volatile storage. The techniques compensate for differences in floating gate coupling effect experienced by non-volatile storage elements on different word lines. An erase of a group of non-volatile storage elements is performed. A set of the non-volatile storage elements are for storing data and at least one of the non-volatile storage elements is a dummy that is not for storing data. The dummy is a neighbor to one of the data non-volatile storage elements. The data non-volatile storage elements are programmed at some point after the erase. Then, a programming voltage is applied to the dummy non-volatile storage element to increase the threshold voltage of the dummy to cause floating gate coupling effect to the neighbor non-volatile storage element to compensate for lesser floating gate coupling effect that the neighbor experienced during programming. | 03-25-2010 |
20100091569 | METHODS OF FORMING FLASH DEVICE WITH SHARED WORD LINES - Word lines of a NAND flash memory array are formed by concentric, rectangular shaped, closed loops that have a width of approximately half the minimum feature size of the patterning process used. The resulting circuits have word lines linked together so that peripheral circuits are shared. Separate erase blocks are established by shield plates. | 04-15-2010 |
20100172187 | ROBUST SENSING CIRCUIT AND METHOD - A sense amplifier is disclosed. One embodiment is a sensing circuit that includes a sensing device and a sense transistor coupled to the sensing device. A first switch that is coupled to the sense transistor and to the sensing device causes the sensing device to be charged to a first voltage that is a function of the threshold voltage of the sense transistor. One or more second switches that are coupled to the sensing device and to a target element. The second switches couple the sensing device to the target element to modify the first voltage on the sensing device and decouple the target element from the sensing device during a sense phase in which the modified first voltage is applied to the sense transistor. A condition of the target element is determined based on whether or not the sense transistor turns on in response to applying the modified first voltage to the sense transistor. | 07-08-2010 |
20100238729 | NON-VOLATILE MEMORY WITH REDUCED LEAKAGE CURRENT FOR UNSELECTED BLOCKS AND METHOD FOR OPERATING SAME - A memory device with reduced leakage current during programming and sense operations, and a method for operating such a memory device. In a non-volatile memory device, current leakage at the drain select gates of NAND strings can occur in unselected blocks when a selected block undergoes a program or read operation, and the bit lines are shared by the blocks. In one approach, in which a common transfer gate driver is provided for both blocks, the drain select gates are pre-charged at an optimum level, which minimizes leakage, and subsequently floated while a program or read voltage is applied to a selected word line in the selected block. In another approach, a separate transfer gate driver is provided for the unselected block so that the optimal select gate voltage can be driven in the unselected block, even while the program or read voltage is applied in the selected block. | 09-23-2010 |
20100240182 | Spacer Patterns Using Assist Layer For High Density Semiconductor Devices - High density semiconductor devices and methods of fabricating the same are provided. Spacer fabrication techniques are utilized to form circuit elements having reduced feature sizes, which in some instances are smaller than the smallest lithographically resolvable element size of the process being used. Spacers are formed that serve as a mask for etching one or more layers beneath the spacers. An etch stop pad layer having a material composition substantially similar to the spacer material is provided between a dielectric layer and an insulating sacrificial layer such as silicon nitride. When etching the sacrificial layer, the matched pad layer provides an etch stop to avoid damaging and reducing the size of the dielectric layer. The matched material compositions further provide improved adhesion for the spacers, thereby improving the rigidity and integrity of the spacers. | 09-23-2010 |
20100270608 | Integrated Circuits And Fabrication Using Sidewall Nitridation Processes - Semiconductor devices are provided with encapsulating films for protection of sidewall features during fabrication processes, such as etching to form isolation regions. In a non-volatile flash memory, for example, a trench isolation process is divided into segments to incorporate an encapsulating film along the sidewalls of charge storage material. A pattern is formed over the layer stack followed by etching the charge storage material to form strips elongated in the column direction across the substrate, with a layer of tunnel dielectric material therebetween. Before etching the substrate, an encapsulating film is formed along the sidewalls of the strips of charge storage material. The encapsulating film can protect the sidewalls of the charge storage material during subsequent cleaning, oxidation and etch processes. In another example, the encapsulating film is simultaneously formed while etching to form strips of charge storage material and the isolation trenches. | 10-28-2010 |
20100273299 | METHOD FOR FABRICATING NON-VOLATILE STORAGE WITH INDIVIDUALLY CONTROLLABLE SHIELD PLATES BETWEEN STORAGE ELEMENTS - A method for fabricating non-volatile storage having individually controllable shield plates between storage elements. The shield plates are formed by depositing a conductive material such as doped polysilicon between storage elements and their associated word lines, and providing contacts for the shield plates. The shield plates reduce electromagnetic coupling between floating gates of the storage elements, and can be used to optimize programming, read and erase operations. In one approach, the shield plates provide a field induced conductivity between storage elements in a NAND string during a sense operation so that source/drain implants are not needed in the substrate. In some control schemes, alternating high and low voltages are applied to the shield plates. In other control schemes, a common voltage is applied to the shield plates. | 10-28-2010 |
20100330806 | Method of forming contact hole arrays using a hybrid spacer technique - One embodiment of the invention provides a method of forming a plurality of contact holes, including forming a first feature and a second feature over an underlying material, forming sidewall spacers on the first and second features, removing the first and second features without removing the sidewall spacers, forming a cover mask at least partially exposing the sidewall spacers, and etching the underlying material using the cover mask and the sidewall spacers as a mask to form the plurality of contact holes. | 12-30-2010 |
20110020992 | Integrated Nanostructure-Based Non-Volatile Memory Fabrication - Nanostructure-based charge storage regions are included in non-volatile memory devices and integrated with the fabrication of select gates and peripheral circuitry. One or more nanostructure coatings are applied over a substrate at a memory array area and a peripheral circuitry area. Various processes for removing the nanostructure coating from undesired areas of the substrate, such as target areas for select gates and peripheral transistors, are provided. One or more nanostructure coatings are formed using self-assembly based processes to selectively form nanostructures over active areas of the substrate in one example. Self-assembly permits the formation of discrete lines of nanostructures that are electrically isolated from one another without requiring patterning or etching of the nanostructure coating. | 01-27-2011 |
20110026327 | BIT-LINE CONNECTIONS FOR NON-VOLATILE STORAGE - Bit line connections for non-volatile storage devices and methods for fabricating the same are disclosed. At least two different types of bit line connections may be used between memory cells and bit lines. The different types of bit line connections may be structurally different from each other as follows. One type of bit line connection may include a metal pad between an upper via and lower via. Another type of bit line connection may include an upper via and lower via, but does not include the metal pad. Three rows of bit line connections may be used to relax the pitch. For example, two rows of bit line connections on the outside may have the metal pad, whereas bit line connections in the middle row do not have the metal pad. | 02-03-2011 |
20110111583 | METHOD OF REDUCING COUPLING BETWEEN FLOATING GATES IN NONVOLATILE MEMORY - A nonvolatile memory array includes floating gates that have an inverted-T shape in cross section along a plane that is perpendicular to the direction along which floating cells are connected together to form a string. Adjacent strings are isolated by shallow trench isolation structures. | 05-12-2011 |
20110159649 | NON-VOLATILE STORAGE WITH SUBSTRATE CUT-OUT AND PROCESS OF FABRICATING - Shallow trench isolation regions are positioned between NAND strings (or other types of non-volatile storage). These isolation regions include sections that form concave cut-out shapes in the substrate for the NAND string (or other types of non-volatile storage). The floating gates (or other charge storage devices) of the NAND strings hang over the sections of the isolation region that form the concave cut-out shape in the substrate. To manufacture such a structure, a two step etching process is used to form the isolation regions. In the first step, isotropic etching is used to remove substrate material in multiple directions, including removing substrate material underneath the floating gates. In the second step, anisotropic etching is used to create the lower part of the isolation region. | 06-30-2011 |
20110188313 | DATA RETENTION OF LAST WORD LINE OF NON-VOLATILE MEMORY ARRAYS - Techniques for operating non-volatile storage compensate for differences in floating gate coupling effect experienced by non-volatile storage elements on different word lines. An erase of a group of non-volatile storage elements is performed. A set of the non-volatile storage elements are for storing data and at least one of the non-volatile storage elements is a dummy that is not for storing data. The dummy is a neighbor to one of the data non-volatile storage elements. The data non-volatile storage elements are programmed at some point after the erase. Then, a programming voltage is applied to the dummy non-volatile storage element to increase the threshold voltage of the dummy to cause floating gate coupling effect to the neighbor non-volatile storage element to compensate for lesser floating gate coupling effect that the neighbor experienced during programming. | 08-04-2011 |
20110229805 | PHOTOMASK WITH ASSIST FEATURES - A photomask for exposure of a semiconductor wafer using dipole illumination and method of manufacturing the same is disclosed. A method of forming a pattern on a semiconductor using the photomask is also disclosed. The photomask may have an array of islands that are used for printing lines using dipole illumination. The photomask may have sub-resolution assist features (SRAF) to assist in printing the lines. The SRAF may include an array of holes. | 09-22-2011 |
20110256679 | NON-VOLATILE STORAGE HAVING A CONNECTED SOURCE AND WELL - A non-volatile storage device is disclosed that includes a set of connected non-volatile storage elements formed on a well, a bit line contact positioned in the well, a source line contact positioned in the well, a bit line that is connected to the bit line contact, and a source line that is connected to the source line contact and the well. | 10-20-2011 |
20110286265 | PROGRAMMING NON-VOLATILE STORAGE WITH SYNCHONIZED COUPLING - A process for programming non-volatile storage is able to achieve faster programming speeds and/or more accurate programming through synchronized coupling of neighboring word lines. The process for programming includes raising voltages for a set of word lines connected a group of connected non-volatile storage elements. The set of word lines include a selected word line, unselected word lines that are adjacent to the selected word line and other unselected word lines. After raising voltages for the set of word lines, the process includes raising the selected word line to a program voltage and raising the unselected word lines that are adjacent to the selected word line to one or more voltage levels concurrently with the raising the selected word line to the program voltage. The program voltage causes at least one of the non-volatile storage elements to experience programming. | 11-24-2011 |
20110299314 | Non-Volatile Memory Having 3d Array of Read/Write Elements with Efficient Decoding of Vertical Bit Lines and Word Lines - A three-dimensional array of memory elements is formed across multiple layers of planes positioned at different distances above a semiconductor substrate. The memory elements reversibly change a level of electrical conductance in response to a voltage difference being applied across them. The three-dimensional array includes a two-dimensional array of pillar lines from the substrate through the multiple layers of planes. A first set of pillar lines acts as local bit lines for accessing the memory elements together with an array of word lines on each plane. A second set of pillar lines is connected to the word lines. An array of metal lines on the substrate is switchable connected to the pillar lines to provide access to the first and second sets of pillar lines, thereby to provide access respectively to the bit lines and word lines of the three-dimensional array. | 12-08-2011 |
20120083124 | Method of Patterning NAND Strings Using Perpendicular SRAF - A lithography mask includes a plurality of patterning features formed on a mask substrate and a first plurality of sub-resolution assist features (SRAFs) formed substantially perpendicular to the patterning features on the mask substrate. | 04-05-2012 |
20120147676 | NON-VOLATILE STORAGE SYSTEM WITH SHARED BIT LINES CONNECTED TO SINGLE SELECTION DEVICE - A non-volatile storage system is disclosed that includes pairs of NAND strings (or other groupings of memory cells) in the same block being connected to and sharing a common bit line. To operate the system, two selection lines are used so that the NAND strings (or other groupings of memory cells) sharing a bit line can be selected at the block level. Both selection lines are connected to a selection gate for each of the NAND strings (or other groupings of memory cells) sharing the bit line. | 06-14-2012 |
20120228691 | PN FLOATING GATE NON-VOLATILE STORAGE ELEMENT - Non-volatile storage elements having a PN floating gate are disclosed herein. The floating gate may have a P− region near the tunnel oxide, and may have an N+ region near the control gate. In some embodiments, a P− region near the tunnel oxide helps provide good data retention. In some embodiments, an N+ region near the control gate helps to achieve a good coupling ratio between the control gate and floating gate. Therefore, programming of non-volatile storage elements is efficient. Also erasing the non-volatile storage elements may be efficient. In some embodiments, having a P− region near the tunnel oxide (as opposed to a strongly doped p-type semiconductor) may improve erase efficiency relative to P+. | 09-13-2012 |
20120243337 | P-/METAL FLOATING GATE NON-VOLATILE STORAGE ELEMENT - Non-volatile storage elements having a P−/metal floating gate are disclosed herein. The floating gate may have a P− region near the tunnel oxide, and may have a metal region near the control gate. A P− region near the tunnel oxide helps provide good data retention. A metal region near the control gate helps to achieve a good coupling ratio between the control gate and floating gate. Therefore, programming of non-volatile storage elements is efficient. Also, erasing the non-volatile storage elements may be efficient. In some embodiments, having a P− region near the tunnel oxide (as opposed to a strongly doped p-type semiconductor) may improve erase efficiency relative to P+. | 09-27-2012 |
20120258387 | METHOD AND MASK FOR ENHANCING THE RESOLUTION OF PATTERNING 2-ROW HOLES - A photolithography mask including a plurality of mask features. Adjacent mask features are separated by a gap and are offset from each other such that individual mask features have one-side dense portions and two-side dense portions. Also a photolithography method that includes a step of providing a substantially opaque mask having N stepped rows of offset, substantially transparent, rectangular mask features, where N is an integer and N≧2. The method also includes illuminating a photoresist layer located over an underlying material with dipole illumination through the substantially transparent, rectangular mask features in the substantially opaque mask to form 2N rows of exposed regions in the photoresist layer. The exposed regions have a substantially elliptical or substantially circular shape when viewed from above the photoresist layer. | 10-11-2012 |
20120314502 | PROGRAMMING NON-VOLATILE STORAGE WITH SYNCHONIZED COUPLING - A process for programming non-volatile storage is able to achieve faster programming speeds and/or more accurate programming through synchronized coupling of neighboring word lines. The process for programming includes raising voltages for a set of word lines connected a group of connected non-volatile storage elements. The set of word lines include a selected word line, unselected word lines that are adjacent to the selected word line and other unselected word lines. After raising voltages for the set of word lines, the process includes raising the selected word line to a program voltage and raising the unselected word lines that are adjacent to the selected word line to one or more voltage levels concurrently with the raising the selected word line to the program voltage. The program voltage causes at least one of the non-volatile storage elements to experience programming. | 12-13-2012 |
20120326220 | Integrated Circuits With Sidewall Nitridation - Semiconductor devices are provided with encapsulating films for protection of sidewall features during fabrication processes, such as etching to form isolation regions. In a non-volatile flash memory, for example, a trench isolation process is divided into segments to incorporate an encapsulating film along the sidewalls of charge storage material. A pattern is formed over the layer stack followed by etching the charge storage material to form strips elongated in the column direction across the substrate, with a layer of tunnel dielectric material therebetween. Before etching the substrate, an encapsulating film is formed along the sidewalls of the strips of charge storage material. The encapsulating film can protect the sidewalls of the charge storage material during subsequent cleaning, oxidation and etch processes. In another example, the encapsulating film is simultaneously formed while etching to form strips of charge storage material and the isolation trenches. | 12-27-2012 |
20130040232 | Method of Patterning NAND Strings Using Perpendicular SRAF - A lithography mask includes a plurality of patterning features formed on a mask substrate and a first plurality of sub-resolution assist features (SRAFs) formed substantially perpendicular to the patterning features on the mask substrate. | 02-14-2013 |
20130070530 | HIGH ENDURANCE NON-VOLATILE STORAGE - A non-volatile storage system is disclosed that includes non-volatile memory cells designed for high endurance and lower retention than other non-volatile memory cells. | 03-21-2013 |
20130107627 | BACK-BIASING WORD LINE SWITCH TRANSISTORS | 05-02-2013 |
20130126957 | 3D Non-Volatile Memory With Metal Silicide Interconnect - A stacked non-volatile memory cell array include cell areas with rows of vertical columns of NAND cells, and an interconnect area, e.g., midway in the array and extending a length of the array. The interconnect area includes at least one metal silicide interconnect extending between insulation-filled slits, and does not include vertical columns of NAND cells. The metal silicide interconnect can route power and control signals from below the stack to above the stack. The metal silicide interconnect can also be formed in a peripheral region of the substrate. Contact structures can extend from a terraced portion of the interconnect to at least one upper metal layer, above the stack, to complete a conductive path from circuitry below the stack to the upper metal layer. Subarrays can be provided in a plane of the array without word line hook-up and transfer areas between the subarrays. | 05-23-2013 |
20130127011 | Passive Devices For 3D Non-Volatile Memory - Passive devices such as resistors and capacitors are provided for a 3D non-volatile memory device. In a peripheral area of a substrate, a passive device includes alternating layers of a dielectric such as oxide and a conductive material such as heavily doped polysilicon or metal silicide in a stack. The substrate includes one or more lower metal layers connected to circuitry. One or more upper metal layers are provided above the stack. Contact structures extend from the layers of conductive material to portions of the one or more upper metal layers so that the layers of conductive material are connected to one another in parallel, for a capacitor, or serially, for a resistor, by the contact structures and the at least one upper metal layer. Additional contact structures can connect the circuitry to the one or more upper metal layers. | 05-23-2013 |
20130130468 | Method For Fabricating Passive Devices For 3D Non-Volatile Memory - A method for fabricating passive devices such as resistors and capacitors for a 3D non-volatile memory device. In a peripheral area of a substrate, alternating layers of a dielectric such as oxide and a conductive material such as heavily doped polysilicon or metal silicide are provided in a stack. The substrate includes one or more lower metal layers connected to circuitry. One or more upper metal layers are formed above the stack. Contact structures are formed which extend from the layers of conductive material to portions of the one or more upper metal layers so that the layers of conductive material are connected to one another in parallel or serially by the contact structures and the at least one upper metal layer. Additional contact structures can connect the circuitry to the one or more upper metal layers. The passive device can be fabricated concurrently with a 3D memory array using common processing steps. | 05-23-2013 |
20130130495 | Method For Fabricating A Metal Silicide Interconnect In 3D Non-Volatile Memory - A method for fabricating a metal silicide interconnect in a stacked 3D non-volatile memory array. A stack of alternating layers of undoped/lightly doped polysilicon and heavily doped polysilicon is formed on a substrate. Memory holes are etched in cell areas of the stack while an interconnect area is protected. Slits are etched in the cell areas and the interconnect areas. A wet etch is performed via the slits or the memory holes in the cell area to remove portions of the undoped/lightly doped polysilicon layers in the cell area, and dielectric is deposited. Silicidation transforms portions of the heavily doped polysilicon layers in the cell area to metal silicide, and transforms portions of the heavily doped and undoped/lightly doped polysilicon layers in the interconnect area to metal silicide. The metal silicide interconnect can be used for routing power and control signals from below the stack to above the stack. | 05-23-2013 |
20130161719 | Integrated Nanostructure-Based Non-Volatile Memory Fabrication - Nanostructure-based charge storage regions are included in non-volatile memory devices and integrated with the fabrication of select gates and peripheral circuitry. One or more nanostructure coatings are applied over a substrate at a memory array area and a peripheral circuitry area. Various processes for removing the nanostructure coating from undesired areas of the substrate, such as target areas for select gates and peripheral transistors, are provided. One or more nanostructure coatings are formed using self-assembly based processes to selectively form nanostructures over active areas of the substrate in one example. Self-assembly permits the formation of discrete lines of nanostructures that are electrically isolated from one another without requiring patterning or etching of the nanostructure coating. | 06-27-2013 |
20130163340 | NON-VOLATILE STORAGE SYSTEM WITH THREE LAYER FLOATING GATE - A non-volatile storage system includes memory cells with floating gates that comprises three layers separated by two dielectric layers (an upper dielectric layer and lower dielectric layer). The dielectric layers may be an oxide layers, nitride layers, combinations of oxide and nitride, or some other suitable dielectric material. The lower dielectric layer is close to the bottom of the floating gate (near interface between floating gate and tunnel dielectric), while the upper dielectric layer is close to top of the floating gate (near interface between floating gate and inter-gate dielectric). | 06-27-2013 |
20130224918 | NON-VOLATILE STORAGE HAVING A CONNECTED SOURCE AND WELL - A non-volatile storage device is disclosed that includes a set of connected non-volatile storage elements formed on a well, a bit line contact positioned in the well, a source line contact positioned in the well, a bit line that is connected to the bit line contact, and a source line that is connected to the source line contact and the well. | 08-29-2013 |
20130270568 | THIN FILM TRANSISTOR - Disclosed herein are thin film transistors (TFTs) and techniques for fabricating TFTs. A major plane of the gate electrode of the TFT may be vertically oriented with respect to a horizontal layer of polysilicon in which the TFT resides. An interface between the gate electrode and gate dielectric may be vertically oriented with respect to a horizontal layer of polysilicon in which the TFT resides. The TFT may have a channel width that is defined by a thickness of the horizontal layer of polysilicon. The TFT may be formed by etching a hole in a layer of polysilicon. Then, a gate electrode and gate dielectric may be formed in the hole by depositing layers of dielectric and conductor material on the sidewall. The body may be formed in the horizontal layer of polysilicon outside the hole. | 10-17-2013 |
20130272069 | 3D NON-VOLATILE STORAGE WITH TRANSISTOR DECODING STRUCTURE - Disclosed herein are 3D stacked memory devices having WL select gates. The 3D stacked memory device could have NAND strings. The WL select gates may be located adjacent to a word line hookup area of a word line plate. The word line plate may be driven by a word line plate driver and may have many word lines. The WL select gates may select individual word lines or groups of word lines. Therefore, smaller units that the entire block may be selected. This may reduce capacitive loading. The WL select gates may include thin film transistors. 3D decoding may be provided in a 3D stacked memory device using the WL select gates. | 10-17-2013 |
20130273700 | FABRICATING 3D NON-VOLATILE STORAGE WITH TRANSISTOR DECODING STRUCTURE - Disclosed herein are techniques for fabricating a 3D stacked memory device having word line (WL) select gates. The bodies of the WL select gates may be formed from the same material (e.g., highly doped polysilicon) that the word lines are formed. Desired doping profiles in a body of a WL select gate may be achieved by various techniques such as counter-doping. The WL select gates may include TFTs that formed by etching holes in the layer in which word lines are formed. Gate electrodes and gate dielectrics may be formed in the holes. Bodies may be formed in the polysilicon outside of the holes. | 10-17-2013 |
20130279256 | Soft Erase Operation For 3D Non-Volatile Memory With Selective Inhibiting Of Passed Bits - An erase operation for a 3D stacked memory device selectively inhibits subsets of memory cells which meet a verify condition as the erase operation progresses. As a result, the faster-erasing memory cells are less likely to be over-erased and degradation is reduced. Each subset of memory cells can be independently erased by controlling a select gate, drain (SGD) transistor line, a bit line or a word line, according to the type of subset. For a SGD line subset or a bit line subset, the SGD line or bit line, respectively, is set at a level which inhibits erase. For a word line subset, the word line voltage is floated to inhibit erase. An inhibit or uninhibit status can be maintained for each subset, and each type of subset can have a different maximum allowable number of fail bits. | 10-24-2013 |
20130279257 | Erase Operation For 3D Non-Volatile Memory With Controllable Gate-Induced Drain Leakage Current - An erase operation for a 3D stacked memory device applies an erase pulse which includes an intermediate level (Vgidl) and a peak level (Verase) to a set of memory cells, and steps up Vgidl in erase iterations of the erase operation. Vgidl can be stepped up when a specified portion of the cells have reached the erase verify level. In this case, a majority of the cells may have reached the erase verify level, such that the remaining cells can benefit from a higher gate-induced drain leakage (GIDL) current to reached the erase verify level. Verase can step up before and, optionally, after Vigdl is stepped up, but remain fixed while Vgidl is stepped. Vgidl can be stepped up until a maximum allowed level, Vgidl_max, is reached. Vgidl may be applied to a drain-side and/or source-side of a NAND string via a bit line or source line, respectively. | 10-24-2013 |
20130301358 | BIT LINE BL ISOLATION SCHEME DURING ERASE OPERATION FOR NON-VOLATILE STORAGE - A system for erasing non-volatile storage system that reduces the voltage across the transistor that interfaces between the sense amplifier and the bit line so that the transistor can be made smaller. Additionally, the use of the lower voltage allows for various components to be positioned closer to each other. The use of smaller components and smaller spaces between components allows the non-volatile storage system to include more memory cells, thereby providing the ability to store more data. | 11-14-2013 |
20130314995 | Controlling Dummy Word Line Bias During Erase In Non-Volatile Memory - A technique for erasing non-volatile memory such as a NAND string which includes non-user data or dummy storage elements. The voltages of the non-user data storage elements are capacitively coupled higher by controlled increases in an erase voltage which is applied to a substrate. The voltages are floated by rendering a pass gate transistor in a non-conductive state, where the pass gate transistor is between a voltage driver and a non-user data storage element. Voltages of select gate transistors can also be capacitively coupled higher. The substrate voltage can be increased in steps and/or as a continuous ramp. In one approach, outer dummy storage elements are floated while inner dummy storage elements are driven. In another approach, both outer and inner dummy storage elements are floated. Write-erase endurance of the storage elements is increased due to reduced charge trapping in the substrate. | 11-28-2013 |
20130322174 | Threshold Voltage Adjustment For A Select Gate Transistor In A Stacked Non-Volatile Memory Device - In a 3D stacked non-volatile memory device, the threshold voltages are evaluated and adjusted for select gate, drain (SGD) transistors at drain ends of strings of series-connected memory cells. To optimize and tighten the threshold voltage distribution, the SGD transistors are read at lower and upper levels of an acceptable range. SGD transistors having a low threshold voltage are subject to programming, and SGD transistors having a high threshold voltage are subject to erasing, to bring the threshold voltage into the acceptable range. The evaluation and adjustment can be repeated such as after a specified number of program-erase cycles of an associated sub-block. The condition for repeating the evaluation and adjustment can be customized for different groups of SGD transistors. Aspects include programming SGD transistors with verify and inhibit, erasing SGD transistors with verify and inhibit, and both of the above. | 12-05-2013 |
20140003150 | SYSTEM TO REDUCE STRESS ON WORD LINE SELECT TRANSISTOR DURING ERASE OPERATION | 01-02-2014 |
20140043911 | Method For Non-Volatile Memory Having 3D Array of Read/Write Elements with Efficient Decoding of Vertical Bit Lines and Word Lines - A three-dimensional array of memory elements is formed across multiple layers of planes positioned at different distances above a semiconductor substrate. The memory elements reversibly change a level of electrical conductance in response to a voltage difference being applied across them. The three-dimensional array includes a two-dimensional array of pillar lines from the substrate through the multiple layers of planes. A first set of pillar lines acts as local bit lines for accessing the memory elements together with an array of word lines on each plane. A second set of pillar lines is connected to the word lines. An array of metal lines on the substrate is switchable connected to the pillar lines to provide access to the first and second sets of pillar lines, thereby to provide access respectively to the bit lines and word lines of the three-dimensional array. | 02-13-2014 |
20140106525 | METHOD OF FORMING PN FLOATING GATE NON-VOLATILE STORAGE ELEMENTS AND TRANSISTOR HAVING N+ GATE - Non-volatile storage elements having a PN floating gate are disclosed herein. The floating gate may have a P− region near the tunnel oxide, and may have an N+ region near the control gate. In some embodiments, a P− region near the tunnel oxide helps provide good data retention. In some embodiments, an N+ region near the control gate helps to achieve a good coupling ratio between the control gate and floating gate. Therefore, programming of non-volatile storage elements is efficient. Also erasing the non-volatile storage elements may be efficient. In some embodiments, having a P− region near the tunnel oxide (as opposed to a strongly doped p-type semiconductor) may improve erase efficiency relative to P+. | 04-17-2014 |
20140119126 | Dynamic Bit Line Bias For Programming Non-Volatile Memory - A program operation for a set of non-volatile storage elements. A count is maintained of a number of program pulses which are applied to an individual storage element in a slow programming mode, and an associated bit line voltage is adjusted based on the count. Different bit line voltages can be used, having a common step size or different steps sizes. As a result, the change in threshold voltage of the storage element within the slow programming mode, with each program pulse can be made uniform, resulting in improved programming accuracy. Latches maintain the count of program pulses experienced by the associated storage element, while in the slow programming mode. The storage element is in a fast programming mode when its threshold voltage is below a lower verify level, and in the slow programming mode when its threshold voltage is between the lower verify level and a higher verify level. | 05-01-2014 |
20140126286 | SINGLE-LEVEL CELL ENDURANCE IMPROVEMENT WITH PRE-DEFINED BLOCKS - Techniques are disclosed for SLC blocks having different characteristics than MLC blocks such that SLC blocks will have high endurance and MLC blocks will have high reliability. A thinner tunnel oxide may be used for memory cells in SLC blocks than for memory cells in MLC blocks. A thinner tunnel oxide in SLC blocks may allow a lower program voltage to be used, which may improve endurance. A thicker tunnel oxide in MLC blocks may improve data retention. A thinner IPD may be used for memory cells in SLC blocks than for memory cells in MLC blocks. A thinner IPD may provide a higher coupling ratio, which may allow a lower program voltage. A lower program voltage in SLC blocks can improve endurance. A thicker IPD in MLC blocks can prevent or reduce read disturb. SLC blocks may have a different number of data word lines than MLC blocks. | 05-08-2014 |
20140133231 | BIT LINE RESISTANCE COMPENSATION - Methods for compensating for variations in bit line resistance in non-volatile memories are described. In some embodiments, use of multiple patterning lithography for forming bit lines may lead to systematic variations in bit line resistance between groups of bit lines within a memory array. For example, in some cases, every fourth bit line of four neighboring (or adjacent) bit lines may be formed differently than the other three bit lines within a group of four neighboring bit lines. In one embodiment, bit line segment swapping may be used between blocks within a memory array in order to mitigate variations in bit line resistance. In another embodiment, each group of adjacent bit line segments may be offset (or staggered) per block such that the local routing necessary to connect bit line segments into bit lines may be simplified. | 05-15-2014 |
20140160848 | SELECT GATE BIAS DURING PROGRAM OF NON-VOLATILE STORAGE - Techniques disclosed herein may prevent program disturb by preventing a select transistor of an unselected NAND string from unintentionally turning on. The Vgs of a select transistor of a NAND string may be lowered from one programming pulse to the next programming pulse multiple times. The select transistor may be a drain side select transistor or a source side select transistor. Progressively lowering the Vgs of the select transistor of an unselected NAND string as programming progresses may prevent the select transistor from unintentionally turning on. Therefore, program disturb is prevented or reduced. Vgs may be lowered by applying a lower voltage to a select line associated with the select transistor. Vgs may be lowered by applying a higher voltage to bit lines associated with the unselected NAND strings as programming progresses. Vgs may be lowered by applying a higher voltage to a common source line as programming progresses. | 06-12-2014 |
20140198575 | Method And Apparatus For Program And Erase Of Select Gate Transistors - Techniques are provided for programming and erasing of select gate transistors in connection with the programming or erasing of a set of memory cells. In response to a program command to program memory cells, the select gate transistors are read to determine whether their Vth is below an acceptable range, in which case the select gate transistors are programmed before the memory cells. Or, a decision can be made to program the select gate transistors based on a count of program-erase cycles, whether a specified time period has elapsed and/or a temperature history of the non-volatile storage device. When an erase command is made to erase memory cells, the select gate transistors are read to determine whether their Vth is above an acceptable range. If their Vth is above the acceptable range, the select gate transistors can be erased concurrently with the erasing of the memory cells. | 07-17-2014 |
20140219027 | Programming Select Gate Transistors And Memory Cells Using Dynamic Verify Level - Programming accuracy is increased for select gate transistors and memory cells by using a dynamic verify voltage which increases from an initial level to a final level during a programming operation. Faster-programming transistors are locked out from programming before slower-programming transistors, but experience program disturb which increases their threshold voltage to a common level with the slower-programming transistors at the conclusion of the programming operation. For programming of memory cells to different target data states, an offset between the initial and final verify levels can be different for each data state. In one approach, the offset is greater for lower target data states. The increases in the dynamic verify voltage can be progressively smaller with each subsequent program-verify iteration of the programming operation. The start of the increase can be adapted to the programming progress or can be at a predetermined program-verify iteration. | 08-07-2014 |
20140247662 | Efficient Smart Verify Method For Programming 3D Non-Volatile Memory - In a programming operation of a 3D stacked non-volatile memory device, an initial set of memory cells on a selected word line layer, involving fewer than all memory cells on a selected word line layer, are programmed first as a test case to determine optimal conditions for programming the remaining memory cells on the selected word line layer. For example, a number of program-verify iterations or loops which are needed to program the initial set of memory cells an initial amount is determined. This loop count is then stored, e.g., within the initial set of memory cells, within the remaining memory cells, within memory cells on a remaining word line layer, or in a data register, and programming of the initial set of memory cells continues to completion. Subsequently, the loop count is retrieved and used to determine an optimal starting program voltage for programming the remaining memory cells. | 09-04-2014 |
20140247666 | DYNAMIC ERASE DEPTH FOR IMPROVED ENDURANCE OF NON-VOLATILE MEMORY - Improving endurance for non-volatile memory by dynamic erase depth is disclosed. A group of memory cells are erased. Then, at least some of the erased memory cells are programmed. Programming the memory cells typically impacts the erase threshold distribution of those memory cells that were intended to stay erased. The erase depth of the next erase can be adjusted based on how the program operation affects the erase threshold distribution. As one example, the upper tail of the erase distribution is measured after programming. The higher the upper tail, the shallower the next erase, in one embodiment. This helps to improve endurance. In one embodiment, the erase depth is adjusted by determining a suitable erase verify level. Rather than (or in addition to) adjusting the erase verify level, the number of erase pulses that are performed after erase verify passes can be adjusted to adjust the erase depth. | 09-04-2014 |
20140247667 | PARTITIONED ERASE AND ERASE VERIFICATION IN NON-VOLATILE MEMORY - A set of memory cells can be erased by individually erasing portions of the set in order to normalize the erase behavior of each memory cell and provide more consistent erase rates. An erase voltage pulse can be applied to the set of memory cells with a first group of cells biased for erase and a second group biased to inhibit erase. The erase depth is made shallower as the device is cycled more. | 09-04-2014 |
20140252454 | VERTICAL BIT LINE TFT DECODER FOR HIGH VOLTAGE OPERATION - A 3D memory array having a vertically oriented thin film transistor (TFT) selection device that has a channel extension, otherwise referred to as a gate/junction offset, is disclosed. The vertically oriented TFT selection device with channel extension serves as a vertical bit line selection device in the 3D memory array. A vertical TFT select device having a channel extension has a high breakdown voltage and low leakage current. The channel extension can be at the top junction or bottom junction of the TFT. Depending on whether the memory elements undergo a forward FORM or reverse FORM, either the bottom or top junction can have the channel extension. This provides for a high voltage junction where needed. | 09-11-2014 |
20140254264 | Defect Or Program Disturb Detection With Full Data Recovery Capability - A programming operation for a set of non-volatile storage elements determines whether the storage elements have been programmed properly after a program-verify test is passed and a program status=pass is issued. Write data is reconstructed from sets of latches associated with the storage elements using logical operations optionally one or more reconstruction read operations. Normal read operations are also performed to obtain read data. A number of mismatches between the read data and the reconstructed write data is determined, and determination is made as to whether re-writing of the write data is required based on the number of the mismatches. | 09-11-2014 |
20140254268 | HYBRID NON-VOLATILE MEMORY CELLS FOR SHARED BIT LINE - A non-volatile storage system includes a plurality of groups of connected non-volatile storage elements. Each group comprises multiple connected data non-volatile storage elements and multiple select gates on a common side of the data non-volatile storage elements. The multiple select gates comprise a first select gate and a second select gate. The first select gate has a first threshold voltage for a first subset of the groups and a second threshold voltage for a second subset of the groups due to active area implantation for the second subset of groups that causes the second threshold voltage to be lower than the first threshold voltage. The second select gate of each group has a programmable threshold voltage. Each of the plurality of bit lines are connected to multiple groups of connected non-volatile storage elements. | 09-11-2014 |
20140254269 | NON-VOLATILE STORAGE WITH SHARED BIT LINES AND FLAT MEMORY CELLS - A non-volatile storage system is disclosed that includes pairs (or another number) of NAND strings (or other groupings of memory cells) in the same block being connected to and sharing a common bit line. By sharing bit lines, less bit lines are needed in the storage system. Using less bit lines reduces the space needed to implement the storage system. Each NAND string will have two drain side select gates. The non-volatile storage system will have two drain side selection lines each connected to one of the two drain side select gates so that the NAND strings sharing a bit line can be individually selected. To allow proper selection of a NAND string using the select gates, the select gates will be subjected to non-volatile programming in order to set the threshold voltage of the select gates to an appropriate level. | 09-11-2014 |
20140254277 | Method And Apparatus For Program And Erase Of Select Gate Transistors - Techniques are provided for programming and erasing of select gate transistors in connection with the programming or erasing of a set of memory cells. In response to a program command to program memory cells, the select gate transistors are read to determine whether their Vth is below an acceptable range, in which case the select gate transistors are programmed before the memory cells. Or, a decision can be made to program the select gate transistors based on a count of program-erase cycles, whether a specified time period has elapsed and/or a temperature history of the non-volatile storage device. When an erase command is made to erase memory cells, the select gate transistors are read to determine whether their Vth is above an acceptable range. If their Vth is above the acceptable range, the select gate transistors can be erased concurrently with the erasing of the memory cells. | 09-11-2014 |
20140254283 | Programming Select Gate Transistors And Memory Cells Using Dynamic Verify Level - Programming accuracy is increased for select gate transistors and memory cells by using a dynamic verify voltage which increases from an initial level to a final level during a programming operation. Faster-programming transistors are locked out from programming before slower-programming transistors, but experience program disturb which increases their threshold voltage to a common level with the slower-programming transistors at the conclusion of the programming operation. For programming of memory cells to different target data states, an offset between the initial and final verify levels can be different for each data state. In one approach, the offset is greater for lower target data states. The increases in the dynamic verify voltage can be progressively smaller with each subsequent program-verify iteration of the programming operation. The start of the increase can be adapted to the programming progress or can be at a predetermined program-verify iteration. | 09-11-2014 |
20140269070 | Compensation For Temperature Dependence Of Bit Line Resistance - Techniques for sensing the threshold voltage of a memory cell during reading and verify operations by compensating for changes, including temperature-based changes, in the resistance of a bit line or other control line. A memory cell being sensed is in a block in a memory array and the block is in a group of blocks. A portion of the bit line extends between the group of blocks and a sense component and has a resistance which is based on the length/distance and the temperature. Various parameters can be varied with temperature and the group of blocks to provide the compensation, including bit line voltage, selected word line voltage, source line voltage, sense time and/or sense current or voltage. | 09-18-2014 |
20140269081 | SOFT ERASE OPERATION FOR 3D NON-VOLATILE MEMORY WITH SELECTIVE INHIBITING OF PASSED BITS - An erase operation for a 3D stacked memory device selectively inhibits subsets of memory cells which meet a verify condition as the erase operation progresses. As a result, the faster-erasing memory cells are less likely to be over-erased and degradation is reduced. Each subset of memory cells can be independently erased by controlling a select gate, drain (SGD) transistor line, a bit line or a word line, according to the type of subset. For a SGD line subset or a bit line subset, the SGD line or bit line, respectively, is set at a level which inhibits erase. For a word line subset, the word line voltage is floated to inhibit erase. An inhibit or uninhibit status can be maintained for each subset, and each type of subset can have a different maximum allowable number of fail bits. | 09-18-2014 |
20140293701 | Adjusting Control Gate Overdrive Of Select Gate Transistors During Programming Of Non-Volatile Memory - In a 3D stacked non-volatile memory device, multiple smaller drain-end selected gate (SGD) transistors replace one larger SGD transistor. The SGD transistors have different control gate overdrive voltages so that, during a programming operation, a discontinuous channel potential is created in an inhibited NAND string. The SGD transistor closest to the bit line has a lower control gate overdrive voltage so that the channel potential under it is lower, and the next SGD transistor has a higher control gate overdrive voltage so that the channel potential under it is higher. The different control gate overdrive voltages can be provided by programming different threshold voltages, or by providing different control gates voltages, for the SGD transistors. Undesirable reductions in a Vsgd window due to drain-induced barrier lowering can be avoided. | 10-02-2014 |
20140293702 | Select Gate Materials Having Different Work Functions In Non-Volatile Memory - In a 3D stacked non-volatile memory device, multiple smaller drain-end selected gate (SGD) transistors replace one larger SGD transistor. The SGD transistors have different work functions in their control gates so that, during a programming operation, a discontinuous channel potential is created in an inhibited NAND string. The SGD transistor closest to the bit line has a higher work function so that the channel potential under it is lower, and the next SGD transistor has a lower work function so that the channel potential under it is higher. The different work functions can be provided by using different control gate materials for the SGD transistors. One option uses p+ polysilicon and n+ polysilicon to provide higher and lower work functions, respectively. Metal or metal silicide can also be used. A single SGD transistor with different control gate materials could also be used. | 10-02-2014 |
20140353573 | METHODS AND SYSTEMS TO REDUCE LOCATION-BASED VARIATIONS IN SWITCHING CHARACTERISTICS OF 3D RERAM ARRAYS - Methods for reducing location-based variations in the switching characteristics of memory cells within a memory array are described. In some cases, the resistance of an embedded resistor within each memory cell may be set to reduce the overall variation in series resistances for the memory cells within a memory array. For example, embedded resistors associated with far-far bits may be set to a lower resistance than embedded resistors associated with near-near bits. An embedded resistor may comprise a layer of polysilicon within a memory cell. Selective ion implantation may be used to reduce the embedded resistor resistance for memory cells within a particular region of the memory array and to form two or more different sets of embedded resistors within the memory array. | 12-04-2014 |
20140362641 | Program And Read Operations For 3D Non-Volatile Memory Based On Memory Hole Diameter - Techniques are provided for programming and reading memory cells in a 3D stacked non-volatile memory device by compensating for variations in a memory hole diameter. The memory hole diameter is smaller at the bottom of the stack, resulting in more severe read disturb. To compensate, programming of memory cells at the lower word line layers is modified. In one approach, threshold voltage (Vth) distributions of one or more data states are narrowed during programming so that a lower read pass voltage can be used in a subsequent sensing operation. A sufficient spacing is maintained between the read pass voltage and the upper tail of the highest data state. The Vth distributions can be downshifted as well. In another approach, the read pass voltage is not lowered, but the lowest programmed state is upshifted to provide spacing from the upper tail of the erased state. | 12-11-2014 |
20140362642 | 3D Non-Volatile Memory With Control Gate Length Based On Memory Hole Diameter - A structure and fabrication process are provided for a 3D stacked non-volatile memory device which compensates for variations in a memory hole diameter. The memory hole diameter is smaller at the bottom of the stack, resulting in more severe read disturb. To compensate, the word line layers are thicker at the bottom of the stack and can increase gradually from the bottom to the top of the stack. As a result, the length of the control gates of the memory cells is greater at the bottom of the stack. The capacitance between the control gate and a charge trapping layer increased in proportion to the length of the control gates. During programming, a narrower threshold voltage (Vth) distribution is achieved for these memory cells. The Vth distributions can be placed closer together and downshifted to allow lowering of a read pass voltage in a subsequent sensing operation, reducing read disturb. | 12-11-2014 |
20140362645 | 3D Non-Volatile Memory With Control Gate Length Based On Memory Hole Diameter - A structure and fabrication process are provided for a 3D stacked non-volatile memory device which compensates for variations in a memory hole diameter. The memory hole diameter is smaller at the bottom of the stack, resulting in more severe read disturb. To compensate, the word line layers are thicker at the bottom of the stack and can increase gradually from the bottom to the top of the stack. As a result, the length of the control gates of the memory cells is greater at the bottom of the stack. The capacitance between the control gate and a charge trapping layer increased in proportion to the length of the control gates. During programming, a narrower threshold voltage (Vth) distribution is achieved for these memory cells. The Vth distributions can be placed closer together and downshifted to allow lowering of a read pass voltage in a subsequent sensing operation, reducing read disturb. | 12-11-2014 |
20140369129 | Method And Apparatus For Program And Erase Of Select Gate Transistors - Techniques are provided for programming select gate transistors in connection with the programming of a set of memory cells. In response to a program command to program memory cells, the select gate transistors are read to determine whether their Vth is below an acceptable range, in which case the select gate transistors are programmed before the memory cells. Or, a decision can be made to program the select gate transistors based on a count of program-erase cycles, whether a specified time period has elapsed and/or a temperature history of the non-volatile storage device. | 12-18-2014 |
20150054046 | 3D Non-Volatile Memory With Metal Silicide Interconnect - A stacked non-volatile memory cell array include cell areas with rows of vertical columns of NAND cells, and an interconnect area, e.g., midway in the array and extending a length of the array. The interconnect area includes at least one metal silicide interconnect extending between insulation-filled slits, and does not include vertical columns of NAND cells. The metal silicide interconnect can route power and control signals from below the stack to above the stack. The metal silicide interconnect can also be formed in a peripheral region of the substrate. Contact structures can extend from a terraced portion of the interconnect to at least one upper metal layer, above the stack, to complete a conductive path from circuitry below the stack to the upper metal layer. Subarrays can be provided in a plane of the array without word line hook-up and transfer areas between the subarrays. | 02-26-2015 |
20150069320 | VERTICAL BIT LINE WIDE BAND GAP TFT DECODER - A 3D memory array having a vertically oriented thin film transistor (TFT) selection device that has a body formed from a wide energy band gap semiconductor is disclosed. The wide energy band gap semiconductor may be an oxide semiconductor, such as a metal oxide semiconductor. As examples, this could be an InGaZnO, InZnO, HfInZnO, or ZnInSnO body. The source and drains can also be formed from the wide energy band gap semiconductor, although these may be doped for better conduction. The vertically oriented TFT selection device serves as a vertical bit line selection device in the 3D memory array. A vertical TFT select device has a high drive current, a high breakdown voltage and low leakage current. | 03-12-2015 |
20150069377 | 3D NON-VOLATILE STORAGE WITH WIDE BAND GAP TRANSISTOR DECODER - Disclosed herein are 3D stacked memory devices having WL select gates that comprises TFTs having bodies formed from a wide band gap semiconductor. The wide energy band gap semiconductor may be an oxide semiconductor, such as a metal oxide semiconductor. As examples, this could be an InGaZnO, InZnO, HfInZnO, or ZnInSnO body. The word lines may be formed from metal, such as tungsten. The 3D stacked memory device could have NAND strings. The TFTs may be formed in the word line layer. The TFT has a high drive current, a high breakdown voltage and low leakage current. | 03-12-2015 |
20150070998 | VREAD BIAS ALLOCATION ON WORD LINES FOR READ DISTURB REDUCTION IN 3D NON-VOLATILE MEMORY - Techniques are provided for sensing memory cells in a 3D stacked non-volatile memory device in a way which reduces read disturb, by using read pass voltages which are adjusted based on variations in a memory hole diameter. The memory cells are in NAND strings which extend in the memory holes. A larger read pass voltage is used for memory cells which are adjacent to wider portions of the memory holes, and a smaller read pass voltage is used for memory cells which are adjacent to narrower portions of the memory holes. This approach reduces the worst-case read disturb. Further, an overall resistance in the NAND string channel may be substantially unchanged so that a reference current used during sensing may be unchanged. The read pass voltage may be set based on a program voltage trim value, which is indicative of programming speed and memory hole diameter. | 03-12-2015 |
20150078090 | 3D Non-Volatile Storage With Transistor Decoding Structure - Disclosed herein are 3D stacked memory devices having WL select gates. The 3D stacked memory device could have NAND strings. The WL select gates may be located adjacent to a word line hookup area of a word line plate. The word line plate may be driven by a word line plate driver and may have many word lines. The WL select gates may select individual word lines or groups of word lines. Therefore, smaller units that the entire block may be selected. This may reduce capacitive loading. The WL select gates may include thin film transistors. 3D decoding may be provided in a 3D stacked memory device using the WL select gates. | 03-19-2015 |