Patent application number | Description | Published |
20110121876 | State retention circuit and method of operation of such a circuit - A state retention circuit is provided comprising a pulse generator which is configured in a non-retention mode of operation to be responsive to a clock signal to periodically assert a pulse, and a storage structure that comprises a storage element for storing state and an isolation structure for responding to the asserted pulse. In particular, the isolation structure is responsive to the asserted pulse to cause the storage element to update its stored state dependent on an input to the storage structure. Conversely, in the absence of the asserted pulse, the isolation structure isolates the storage element from the input. The pulse generator can be driven by a retention control signal to enter a retention mode of operation, during which it does not assert the pulse irrespective of changes in the clock signal. As a result, the isolation structure isolates the storage element from the input during the retention mode of operation, causing the storage element to retain its stored state prior to entry of the retention mode of operation irrespective of changes in the clock signal or changes in the input during the retention mode of operation. Such a design provides a clock independent pulse retention storage structure of small area, high performance and low energy consumption. | 05-26-2011 |
20120013319 | Power control apparatus and method - A power control apparatus for controlling a supply voltage for an associated circuit comprises a power input for receiving an input voltage and a power output for supplying the supply voltage to the circuit. A switch device is provided with a first terminal coupled to the power input, a second terminal coupled to the power output and a control terminal for receiving a sleep select signal. A control device selectively configures the switch device to act as either a power gating switch, in which the switch device is responsive to the sleep select signal to select whether or not to supply the input voltage to the power output; or a retention switch in which a voltage difference is formed between the power input and the power input and the switch device supplies a retention voltage to the power output, the retention voltage being different to the input voltage. | 01-19-2012 |
20120286824 | Supplying a clock signal and a gated clock signal to synchronous elements - A clock gating circuitry unit for supplying either a clock signal or a predetermined gated value to a plurality of synchronous elements within an integrated circuit is disclosed. The clock gating circuitry is configured to receive a clock signal and to output an output signal comprising either the clock signal or the predetermined gated value. The clock gating circuitry unit receives a clock signal, a clock enable signal having either an enable value indicating the plurality of synchronous elements to are currently functional and are to be clocked, or a disable value indicating the plurality of synchronous elements are currently not required and are not to be clocked, and a power mode signal having either a low power value indicating entry to a low power mode in which at least a portion of the plurality of synchronous elements are powered to retain data and are not clocked and at least a further portion of the plurality of synchronous elements are powered down, or a functional mode value indicating the plurality of synchronous elements are to be powered. The clock gating unit has logic circuitry that is configured in response to the clock enable signal having the enable value and to the low power mode signal having the functional mode value to output the clock signal and in response to at least one of the clock enable signal having the disable value and the low power mode signal having the low power value to output the predetermined gated value. | 11-15-2012 |
20130064019 | DATA STORAGE CIRCUIT THAT RETAINS STATE DURING PRECHARGE - A data storage circuit for receiving and holding a data value includes an input stage configured to receive a data value in response to the precharge phase changing to an evaluation phase and to hold the data value during the evaluation phase. An output stage has an output latching element for holding the value, two switching devices for updating the output latching element and an output. The switching devices each being controlled by respective signals from dual data lines, wherein, in response to the data value held in the input stage being a logical one, the first switching device updates the output latching element with a value indicative of the logical one and in response to the data value held in the input stage being a logical zero, the second switching device updates the output latching element with a value indicative of the logical zero. | 03-14-2013 |
20140115554 | METHOD OF GENERATING A LAYOUT OF AN INTEGRATED CIRCUIT COMPRISING BOTH STANDARD CELLS AND AT LEAST ONE MEMORY INSTANCE - A method of generating a layout of an integrated circuit is disclosed, the layout incorporating both standard cells and at least one memory instance generated by a memory compiler to define a memory device of the integrated circuit. Input data is received specifying one or more properties of a desired memory instance. The memory compiler generates the desired memory instance based on the input data and using the specified memory architecture. A standard cell library is provided. The memory compiler references at least one property of the standard cell library in order to generate the desired memory instance. The layout is then generated by populating standard cell rows with standard cells selected from the standard cell library in order to provide the functional components required by the integrated circuit, and integrating into the layout the desired memory instance provided by the memory compiler. | 04-24-2014 |
20150349760 | DATA AND CLOCK SIGNAL VOLTAGES WITHIN AN INTEGRATED CIRCUIT - An integrated circuit | 12-03-2015 |
20150370953 | VIA PLACEMENT WITHIN AN INTEGRATED CIRCUIT - An integrated circuit layout | 12-24-2015 |
20150371959 | POWER GRID CONDUCTOR PLACEMENT WITHIN AN INTEGRATED CIRCUIT - An integrated circuit | 12-24-2015 |