Patent application number | Description | Published |
20110206061 | Individual Bit Timeslot Granular, Input Status Adaptive Multiplexing - Systems and methods enable adaptive, single bit-timeslot granular digital multiplexing capable of automatically and dynamically selecting an appropriate input bit from a set of alternative input ports, based on a current status of the alternative inputs. The invention enables input-status-adaptive, dynamic multiplexing of individual bits from multiple, e.g. byte-wide, input ports onto, e.g. a byte-wide, multiplexer output. An input status adaptive, dynamic, bit-granular M-by-M digital cross-connect can be formed out of an arrangement of M (an integer) instances of the input-controllable adaptive M:1 multiplexers. An application is a synchronous, digital network channel that can be dynamically shared, even at a single bit time-slot granularity, among multiple path sources, which furthermore can be located even at different network nodes. Such multi-source-bus configurations of adaptive-multiplexed network channels enable allocating network resources dynamically based on real-time data packet demand variations, thereby maximizing the network throughput for bursty data traffic. | 08-25-2011 |
20130081044 | Task Switching and Inter-task Communications for Multi-core Processors - The invention provides hardware based techniques for switching processing tasks of software programs for execution on a multi-core processor. Invented techniques involve a hardware logic based controller for assigning, adaptive to program processing loads, tasks for processing by cores of a multi-core fabric as well as configuring a set of multiplexers to appropriately interconnect cores of the fabric and program task specific segments at fabric memories, to arrange efficient inter-task communication as well as transferring of activating and de-activating task memory images among the multi-core fabric. The invention thereby provides an efficient, hardware-automated runtime operating system for multi-core processors, minimizing any need to use processing capacity of the cores for traditional operating system software functions. Additionally, such low overhead hardware based operating system for multi-core processors provides significant cost-efficiency and performance advantages, including data processing throughput maximization across all programs dynamically sharing a given multi-core processor, and hardware based security. | 03-28-2013 |
20130145021 | Intelligent Network Alarm Status Monitoring - Systems and methods enable automated, transparent and efficiently scalable alarm monitoring, display, notification, redundant alarm suppression and root-defect resolution in telecom networks, resulting in transparent visibility with intuitive navigation from a network management GUI down to the network element hardware status registers of concern. A logical alarm propagation hierarchy enables efficient root defect resolution in large networks with extensive amounts of individual defects capable of causing alarms, based on hyperlinked navigation from top-level NE alarm indicators down to bottom-level defect status registers. Un-monitored defects (e.g., non-service affecting defects) are prevented from causing unnecessary alarms, and alerts are produced to notify the network operations staff of new NE alarms. Techniques are used to minimize the frequency of such alarm notifications while providing a comprehensive and clear view of the network alarm status, even under heavy loads of defect activity. | 06-06-2013 |
20130239122 | Efficient Network and Memory Architecture for Multi-core Data Processing System - The invention provides hardware logic based techniques for a set of processing tasks of a software program to efficiently communicate with each other while running in parallel on an array of processing cores of a multi-core data processing system dynamically shared among a group of software programs. These inter-task communication techniques comprise, by one or more task of the set, writing their inter-task communication information to a memory segment of other tasks of the set at the system memories, as well as reading inter-task communication information from their own segments at the system memories. The invention facilitates efficient inter-task communication on a multi-core fabric, without any of the communications tasks needing to know whether and at which core in the fabric any other task is executing at any given time. The invention thus enables flexibly and efficiently running any task of any program at any core of the fabric. | 09-12-2013 |
20140032891 | Direct Binary File Transfer based Network Management System Free of Messaging, Commands and Data Format Conversions - Telecommunication network management operations are performed based on accessing network management data (NMD) files via GUIs and general purpose computers including a network management system (NMS) server, and automatic routines for transferring binary NMD files between the general purpose computers and remote network elements (NEs) being managed. A system user produces configuration files at the NMS server for NEs using a network management GUI, and the hardware of NEs automatically complete the network management operations indicated by the NMD files transferred to them from the NMS server and produce their status files to the NMS server. The network management GUI displays network status based on the latest NE status files at the NMS server. This provides direct, binary file transfer based NMS communication that avoids the complexity and restrictions of intermediate messaging protocols or transaction languages and conversions thereof. | 01-30-2014 |
20140075154 | Task Switching and Inter-task Communications for Multi-core Processors - The invention provides hardware based techniques for switching processing tasks of software programs for execution on a multi-core processor. Invented techniques involve a hardware logic based controller for assigning, adaptive to program processing loads, tasks for processing by cores of a multi-core fabric as well as configuring a set of multiplexers to appropriately interconnect cores of the fabric and program task specific segments at fabric memories, to arrange efficient inter-task communication as well as transferring of activating and de-activating task memory images among the multi-core fabric. The invention thereby provides an efficient, hardware-automated runtime operating system for multi-core processors, minimizing any need to use processing capacity of the cores for traditional operating system software functions. Additionally, such low overhead hardware based operating system for multi-core processors provides significant cost-efficiency and performance advantages, including data processing throughput maximization across all programs dynamically sharing a given multi-core processor, and hardware based security. | 03-13-2014 |
20140137133 | Maximizing Throughput of Multi-user Parallel Data Processing Systems - The invention provides systems and methods for maximizing revenue generating throughput of a multi-user parallel data processing platform across a set of users of the service provided with the platform. The invented techniques, for any given user contract among the contracts supported by the platform, and on any given billing assessment period, determine a level of a demand for the capacity of the platform associated with the given contract that is met by a level of access to the capacity of the platform allocated to the given contract, and assess billables for the given contract at least in part based on such met demand and a level of assured access to the capacity of the platform associated with the given contract, as well as billing rates, applicable for the given billing assessment period, for the met demand and the level of assured access associated with the given contract. | 05-15-2014 |
20140149993 | Application Load Adaptive Multi-stage Parallel Data Processing Architecture - Systems and methods provide an extensible, multi-stage, realtime application program processing load adaptive, manycore data processing architecture shared dynamically among instances of parallelized and pipelined application software programs, according to processing load variations of said programs and their tasks and instances, as well as contractual policies. The invented techniques provide, at the same time, both application software development productivity, through presenting for software a simple, virtual static view of the actually dynamically allocated and assigned processing hardware resources, together with high program runtime performance, through scalable pipelined and parallelized program execution with minimized overhead, as well as high resource efficiency, through adaptively optimized processing resource allocation. | 05-29-2014 |
20140173246 | SCHEDULING APPLICATION INSTANCES TO CONFIGURABLE PROCESSING CORES BASED ON APPLICATION REQUIREMENTS AND RESOURCE SPECIFICATION - Systems and methods provide a processing task load and type adaptive manycore processor architecture, enabling flexible and efficient information processing. The architecture enables executing time variable sets of information processing tasks of differing types on their assigned processing cores of matching types. This involves: for successive core allocation periods (CAPs), selecting specific processing tasks for execution on the cores of the manycore processor for a next CAP based at least in part on core capacity demand expressions associated with the processing tasks hosted on the processor, assigning the selected tasks for execution at cores of the processor for the next CAP so as to maximize the number of processor cores whose assigned tasks for the present and next CAP are associated with same core type, and reconfiguring the cores so that a type of each core in said array matches a type of its assigned task on the next CAP. | 06-19-2014 |
20140223446 | Application Load and Type Adaptive Manycore Processor Architecture - Systems and methods provide a processing task load and type adaptive manycore processor architecture, enabling flexible and efficient information processing. The architecture enables executing time variable sets of information processing tasks of differing types on their assigned processing cores of matching types. This involves: for successive core allocation periods (CAPs), selecting specific processing tasks for execution on the cores of the manycore processor for a next CAP based at least in part on core capacity demand expressions associated with the processing tasks hosted on the processor, assigning the selected tasks for execution at cores of the processor for the next CAP so as to maximize the number of processor cores whose assigned tasks for the present and next CAP are associated with same core type, and reconfiguring the cores so that a type of each core in said array matches a type of its assigned task on the next CAP. | 08-07-2014 |
20140237478 | System and Method for Input Data Load Adaptive Parallel Processing - Systems and methods provide an extensible, multi-stage, realtime application program processing load adaptive, manycore data processing architecture shared dynamically among instances of parallelized and pipelined application software programs, according to processing load variations of said programs and their tasks and instances, as well as contractual policies. The invented techniques provide, at the same time, both application software development productivity, through presenting for software a simple, virtual static view of the actually dynamically allocated and assigned processing hardware resources, together with high program runtime performance, through scalable pipelined and parallelized program execution with minimized overhead, as well as high resource efficiency, through adaptively optimized processing resource allocation. | 08-21-2014 |
20140237481 | LOAD BALANCER FOR PARALLEL PROCESSORS - Invented systems and methods provide a scalable architecture and hardware logic algorithms for intelligent, realtime load balancing of incoming processing work load among instances of a number of application programs hosted on parallel arrays of manycore processors, which can be dynamically shared among the hosted applications according to incoming processing data load variations for each of the application instances as well as the processing capacity entitlements of the individual applications. | 08-21-2014 |
20150058857 | Concurrent Program Execution Optimization - An architecture for a load-balanced groups of multi-stage manycore processors shared dynamically among a set of software applications, with capabilities for destination task defined intra-application prioritization of inter-task communications (ITC), for architecture-based ITC performance isolation between the applications, as well as for prioritizing application task instances for execution on cores of manycore processors based at least in part on which of the task instances have available for them the input data, such as ITC data, that they need for executing. | 02-26-2015 |