Patent application number | Description | Published |
20100158005 | System-On-a-Chip and Multi-Chip Systems Supporting Advanced Telecommunication Functions - A system-on-chip integrated circuit (and multi-chip systems based thereon) that includes a bridge interface that provides transparent bridging of data communicated between integrated circuits. | 06-24-2010 |
20100158023 | System-On-a-Chip and Multi-Chip Systems Supporting Advanced Telecommunication Functions - A system-on-chip integrated circuit (and multi-chip systems based thereon) that includes a bridge interface that employs data scrambling and error correction on data communicated between integrated circuits. | 06-24-2010 |
20100161938 | System-On-A-Chip Supporting A Networked Array Of Configurable Symmetric Multiprocessing Nodes - An integrated circuit having an array of programmable processing elements linked by an on-chip communication network. Each processing element includes a plurality of processing cores, a local memory, and thread scheduling means for scheduling execution of threads on the processing cores of the given processing element. The thread scheduling means assigns threads to the processing cores of the given processing element in a configurable manner. The configuration of the thread scheduling means defines one or more logical symmetric multiprocessors for executing threads on the given processing element. A logical symmetric multiprocessor is realized by a defined set of processing cores assigned to a group of threads executing on the given processing element. | 06-24-2010 |
20100162265 | System-On-A-Chip Employing A Network Of Nodes That Utilize Logical Channels And Logical Mux Channels For Communicating Messages Therebetween - An integrated circuit with an array of nodes linked by an on-chip communication network. Messages are communicated between nodes utilizing logical channels representing hardware resources at the associated nodes. A given logical channel is associated with a receiver node and a transmitter node. A set of logical channels are associated with a logical mux channel. The nodes are adapted to carry out operations utilizing a given logical mux channel associated therewith in order to identify a logical channel that is associated with the given logical mux channel and that has a predetermined ready state. In the preferred embodiment, the operations are invoked by a calling thread that is blocked in the event that no logical channel associated with the given logical mux channel has a predetermined ready state. The calling thread is then reactivated in the event that at least one logical channel associated with the given logical mux channel transitions to the predetermined ready state. Preferably, the nodes include a recirculation queue and logic that stores event messages in the recirculation queue. Each given event message provides an indication that an identified logical channel associated with an identified logical mux channel has transitioned to the predetermined ready state. The logic processes the recirculation queue to reactivate calling threads in accordance with the event messages stored therein. The operations temporarily remove the identified logical channel from the given logical mux channel such that the identified local channel behaves like an independent logic channel. The operations that identify the logical channel associated with the given logical mux channel are fair between all logical channels that are associated with the given logical mux channel. | 06-24-2010 |
20100191814 | System-On-A-Chip Employing A Network Of Nodes That Utilize Receive Side Flow Control Over Channels For Messages Communicated Therebetween - An integrated circuit an array of nodes linked by an on-chip communication network. Messages are communicated between nodes utilizing logical channels representing hardware resources at the associated nodes. A given logical channel is associated with a receiver node and a transmitter node. The receiver node is adapted to send flow control messages to the transmitter node. The flow control messages include credits that identify hardware resources of the receiver node that are available for receiving messages over the given logical channel. The transmitter node is adapted to maintain a running total of the credits included as part of the flow control messages communicated from the receiver node and to initiate transmission of messages to the receiver node in accordance with the running total of credits maintained at the transmitter node. In the preferred embodiment, the transmitter node is adapted to initiate transmission of a message to the receiver node only if the total number of credits maintained at the transmitter node is sufficient to store the message at the receiver node. A given credit can include an address generated by a receiver node and representing an address in the local memory of the receiver node for storing data. The transmitter node transmits the address of the given credit to the receiver node for storing data therein. | 07-29-2010 |
20100191911 | System-On-A-Chip Having an Array of Programmable Processing Elements Linked By an On-Chip Network with Distributed On-Chip Shared Memory and External Shared Memory - An integrated circuit having an array of programmable processing elements and a memory interface linked by an on-chip communication network. Each processing element includes a plurality of processing cores and a local memory. The memory interface block is operably coupled to external memory and to the on-chip communication network. The memory interface supports accessing the external memory in response to messages communicated from the processing elements of the array over the on-chip communication network. A portion of the local memory for a plurality of the processing elements of the array as well as a portion of the external memory are both allocated to store data shared by a plurality of processing elements of the array during execution of programmed operations distributed thereon. | 07-29-2010 |