Patent application number | Description | Published |
20080218201 | CML DELAY CELL WITH LINEAR RAIL-TO-RAIL TUNING RANGE AND CONSTANT OUTPUT SWING - A current mode logic (CML) delay cell with linear rail-to-rail tuning range and constant output swing. The CML delay cell can include a tuning voltage input on a first and second transistor, contributing to a CML delay cell load, and a bias voltage input on a third transistor, as a current source I | 09-11-2008 |
20080246522 | PHASE LOCKED LOOP AND METHOD FOR ADJUSTING THE FREQUENCY AND PHASE IN THE PHASE LOCKED LOOP - A phase locked loop (PLL) which includes a phase frequency detector coupled with a time to digital converter capable of comparing a reference signal with an oscillator signal and generating a digital value representing the phase difference between the reference signal and the oscillator signal. The PLL further includes a state machine for phase acquisition that is capable of generating a control value depending on the digital value, and a controllable oscillator that is capable of generating the oscillator signal depending on the control value. | 10-09-2008 |
20090033401 | Level Shifting Circuit With Symmetrical Topology - A shifter circuit includes a pair of feed forward sections and a pair of feedback sections. The sections are arranged and coupled to form a balanced symmetrical topology. The feed forward sections each include inverter pairs of PMOS and NMOS devices. The feedback sections each include a pair of cross-coupled devices. A pair of output nodes are operatively positioned between the pair of feedback sections. A method for using the circuit to generate output signals at respective output ports is also disclosed. | 02-05-2009 |
20090039929 | Method to Reduce Static Phase Errors and Reference Spurs in Charge Pumps - A phase-locked-loop (PLL) circuit, that includes: a differential phase-frequency detector, a charge pump and at least one logical gate disposed therebetween for providing cancellation of pulses of a substantially equivalent value output by the detector to the charge pump; wherein the at least one logical gate receives the detector output signals and generates control signals for the charge pump such that the pulses of substantially equivalent value are eliminated. | 02-12-2009 |
20090201097 | CONTINUOUSLY TUNABLE INDUCTOR AND METHOD TO CONTINUOUSLY TUNE AN INDUCTOR - A continuously tunable inductor with an inductive-capacitive (LC) voltage controlled oscillator (VCO) having a primary coil. The inductor includes a separate isolated secondary coil, a set of transistors composing a closed loop with the secondary coil, a magnetic coupling between the primary coil of the LC VCO and the secondary coil, an electrical coupling between the LC VCO and the set of transistors composing a closed loop with the secondary coil, and means for electric current injection into the closed loop. Such an inductor can be tuned by modulating a mutual inductance, which is magnetically and electrically coupled with the LC VCO by injection of an electric current (I | 08-13-2009 |
20090201100 | INDUCTOR COMBINING PRIMARY AND SECONDARY COILS WITH PHASE SHIFTING - An inductor including a primary coil coaxially arranged and operated in parallel with isolated secondary coils each including at least one loop winding with two open-circuited ports. At least one phase shifting device is arranged between open-circuited ports of at least one secondary coil. A method to operate an inductor by combining primary and secondary coils with phase shifting devices to get a wide tuning range is also provided. The method includes the step of phase shifting open-circuited ports of at least one secondary coil. | 08-13-2009 |
20090201101 | INDUCTOR AND METHOD OF OPERATING AN INDUCTOR BY COMBINING PRIMARY AND SECONDARY COILS WITH COUPLING STRUCTURES - An inductor and method of operating the inductor by combining primary and secondary coils with passive coupling, active parallel, or active cross-coupling structures. The first includes at least one passive coupling structure having at least one coupling coil arranged between a primary coil and at least one of the secondary coils and/or between two of the secondary coils. The second includes an active coupling structure arranged between a primary coil and at least one secondary coil and/or between at least two of the secondary coils, to selectively parallel couple the primary coil and one of the secondary coils and/or at least two of the secondary coils. The third includes an active coupling structure to selectively cross couple a primary coil and at least one of the secondary coils and/or to selectively cross couple at least two of the secondary coils. | 08-13-2009 |
20090243702 | VARACTOR BANK SWITCHING BASED ON NEGATIVE CONTROL VOLTAGE GENERATION - A method and apparatus for varactor bank switching for a voltage controlled oscillator is disclosed. Varactor bank switching involves generating a negative bias voltage signal as a control signal for a varactor bank switch in an off-state, the varactor bank switch comprising a pass-gate circuit including switching transistors. Generating the negative bias voltage signal includes employing an active rectifier circuit running at the speed of an oscillation signal, the negative bias voltage signal maintaining the gate-source voltage of the pass-gate circuit below a threshold voltage to prevent said switching transistors from becoming conductive in an off-state. | 10-01-2009 |
20090243743 | VARACTOR BANK SWITCHING BASED ON ANTI-PARALLEL BRANCH CONFIGURATION - A system and apparatus for varactor bank switching for a voltage controlled oscillator, is disclosed. Varactor bank switching involves partitioning a varactor bank switch into two anti-parallel branches, wherein each branch comprises a pass-gate circuit that is series-connected to a fixed varactor or capacitor; and maintaining an output common mode voltage of an actual oscillator signal at the varactor-side terminal of each pass-gate circuit, such that a threshold voltage of the switch transistor in the pass-gate circuit is not exceeded and the switch remains in an off-state. | 10-01-2009 |
20090323875 | Method for Data Synchronization - A method, apparatus, and system for a data synchronizer/serial link receiver that performs the alignment of the sampling clock used to retime asynchronous customer data by the application of a negative delay onto the system clock whereas the value of the applied negative delay is derived from the analysis of a temperature code obtained by a tapped delay line in conjunction with the application of preceding replica delay lines for the in-phase and quadrature clock signals. | 12-31-2009 |
20120025888 | Drive Strength Control of Phase Rotators - A phase rotator includes a phase selector stage operative to receive a clock signal and output a first phase and a second phase of the clock signal, a slew rate control stage including a first pass gate circuit operative to control a slew rate of the first phase of the clock signal and a second pass gate circuit operative to control a slew rate of the second phase of the clock signal, and a phase blending stage operative to combine the first phase with the second phase of the clock signal and output a phase rotated signal. | 02-02-2012 |
20120243599 | Pipelining and Sub-Rate Operation for Memory Links - A system includes a memory hub chip including a Tomlinson-Harashima precoding (THP) equalizer portion operative to perform transmitter equalization at the memory hub chip and send data from to a memory chip. | 09-27-2012 |
20120327995 | Pipelining and Sub-Rate Operation for Memory Links - A method for sending data to a memory chip includes receiving data at a data transmitter disposed on a memory hub chip, applying Tomlinson-Harashima precoding (THP) equalization to the data prior to transmitting the data; and transmitting the data from the transmitter to a memory chip. | 12-27-2012 |
20130021129 | INDUCTOR COMBINING PRIMARY AND SECONDARY COILS WITH PHASE SHIFTING - An inductor including a primary coil coaxially arranged and operated in parallel with isolated secondary coils each including at least one loop winding with two open-circuited ports. At least one phase shifting device is arranged between open-circuited ports of at least one secondary coil. A method to operate an inductor by combining primary and secondary coils with phase shifting devices to get a wide tuning range is also provided. The method includes the step of phase shifting open-circuited ports of at least one secondary coil. | 01-24-2013 |
20140028363 | PHASE ROTATOR BASED ON VOLTAGE REFERENCING - A phase rotator based on voltage referencing is disclosed. A voltage signal is generated that is proportional to the phase difference between two input signals. The voltage signal is then used as the upper voltage limit for a digital-to-analog converter (DAC). The DAC is programmable via an input vector to generate a DAC output. The DAC output is used to generate a phase rotated (phase shifted) output, which is at an intermediate phase between the two input signals. | 01-30-2014 |
20140035643 | EQUALIZED RISE AND FALL SLEW RATES FOR A BUFFER - Aspects of the invention provide for equalizing rise and fall slew rates at an output for a buffer. In one embodiment, a method includes: measuring, simultaneously, rise and fall slew rates at an input of the buffer and rise and fall slew rates at the output of the buffer; generating a slew reference based on at least one of the rise slew rate or the fall slew rate at the input of the buffer; comparing the rise slew rate and the fall slew rate at the output of the buffer to the slew reference; and generating at least one of a rise control signal or a fall control signal for adjusting at least one of the rise slew rate or the fall slew rate at the output of the buffer. | 02-06-2014 |
20150070069 | LEVEL SHIFTER WITH BUILT-IN LOGIC FUNCTION FOR REDUCED DELAY - A method and circuit for implementing a level shifter with built-in-logic function for reduced delay. The circuit including at least one set of inputs from a first power supply domain. The circuit further including at least two cross coupled field effect transistors (FETs) connected to a second power supply domain. The circuit further including a true logic gate connected to the first power supply domain and the at least two cross coupled FETs. The true logic gate being configured to generate a logic function based on the at least one set of inputs. The circuit further including a complementary logic gate connected to the first power supply domain and the at least two cross coupled FETs. The complementary logic gate being configured to generate a complement of the logic function based on the at least one set of inputs. | 03-12-2015 |